diff options
Diffstat (limited to 'chromium/v8/src/mips/assembler-mips.h')
| -rw-r--r-- | chromium/v8/src/mips/assembler-mips.h | 140 |
1 files changed, 70 insertions, 70 deletions
diff --git a/chromium/v8/src/mips/assembler-mips.h b/chromium/v8/src/mips/assembler-mips.h index d9ef46cd014..2ba3ef7166f 100644 --- a/chromium/v8/src/mips/assembler-mips.h +++ b/chromium/v8/src/mips/assembler-mips.h @@ -37,9 +37,10 @@ #define V8_MIPS_ASSEMBLER_MIPS_H_ #include <stdio.h> -#include "assembler.h" -#include "constants-mips.h" -#include "serialize.h" + +#include "src/assembler.h" +#include "src/mips/constants-mips.h" +#include "src/serialize.h" namespace v8 { namespace internal { @@ -76,6 +77,16 @@ struct Register { static const int kSizeInBytes = 4; static const int kCpRegister = 23; // cp (s7) is the 23rd register. +#if defined(V8_TARGET_LITTLE_ENDIAN) + static const int kMantissaOffset = 0; + static const int kExponentOffset = 4; +#elif defined(V8_TARGET_BIG_ENDIAN) + static const int kMantissaOffset = 4; + static const int kExponentOffset = 0; +#else +#error Unknown endianness +#endif + inline static int NumAllocatableRegisters(); static int ToAllocationIndex(Register reg) { @@ -386,7 +397,15 @@ class Operand BASE_EMBEDDED { // Class MemOperand represents a memory operand in load and store instructions. class MemOperand : public Operand { public: + // Immediate value attached to offset. + enum OffsetAddend { + offset_minus_one = -1, + offset_zero = 0 + }; + explicit MemOperand(Register rn, int32_t offset = 0); + explicit MemOperand(Register rn, int32_t unit, int32_t multiplier, + OffsetAddend offset_addend = offset_zero); int32_t offset() const { return offset_; } bool OffsetIsInt16Encodable() const { @@ -400,64 +419,6 @@ class MemOperand : public Operand { }; -// CpuFeatures keeps track of which features are supported by the target CPU. -// Supported features must be enabled by a CpuFeatureScope before use. -class CpuFeatures : public AllStatic { - public: - // Detect features of the target CPU. Set safe defaults if the serializer - // is enabled (snapshots must be portable). - static void Probe(); - - // Check whether a feature is supported by the target CPU. - static bool IsSupported(CpuFeature f) { - ASSERT(initialized_); - return Check(f, supported_); - } - - static bool IsFoundByRuntimeProbingOnly(CpuFeature f) { - ASSERT(initialized_); - return Check(f, found_by_runtime_probing_only_); - } - - static bool IsSafeForSnapshot(CpuFeature f) { - return Check(f, cross_compile_) || - (IsSupported(f) && - (!Serializer::enabled() || !IsFoundByRuntimeProbingOnly(f))); - } - - static bool VerifyCrossCompiling() { - return cross_compile_ == 0; - } - - static bool VerifyCrossCompiling(CpuFeature f) { - unsigned mask = flag2set(f); - return cross_compile_ == 0 || - (cross_compile_ & mask) == mask; - } - - private: - static bool Check(CpuFeature f, unsigned set) { - return (set & flag2set(f)) != 0; - } - - static unsigned flag2set(CpuFeature f) { - return 1u << f; - } - -#ifdef DEBUG - static bool initialized_; -#endif - static unsigned supported_; - static unsigned found_by_runtime_probing_only_; - - static unsigned cross_compile_; - - friend class ExternalReference; - friend class PlatformFeatureScope; - DISALLOW_COPY_AND_ASSIGN(CpuFeatures); -}; - - class Assembler : public AssemblerBase { public: // Create an assembler. Instructions and relocation information are emitted @@ -517,7 +478,34 @@ class Assembler : public AssemblerBase { // Read/Modify the code target address in the branch/call instruction at pc. static Address target_address_at(Address pc); - static void set_target_address_at(Address pc, Address target); + static void set_target_address_at(Address pc, + Address target, + ICacheFlushMode icache_flush_mode = + FLUSH_ICACHE_IF_NEEDED); + // On MIPS there is no Constant Pool so we skip that parameter. + INLINE(static Address target_address_at(Address pc, + ConstantPoolArray* constant_pool)) { + return target_address_at(pc); + } + INLINE(static void set_target_address_at(Address pc, + ConstantPoolArray* constant_pool, + Address target, + ICacheFlushMode icache_flush_mode = + FLUSH_ICACHE_IF_NEEDED)) { + set_target_address_at(pc, target, icache_flush_mode); + } + INLINE(static Address target_address_at(Address pc, Code* code)) { + ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL; + return target_address_at(pc, constant_pool); + } + INLINE(static void set_target_address_at(Address pc, + Code* code, + Address target, + ICacheFlushMode icache_flush_mode = + FLUSH_ICACHE_IF_NEEDED)) { + ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL; + set_target_address_at(pc, constant_pool, target, icache_flush_mode); + } // Return the code target address at a call site from the return address // of that call in the instruction stream. @@ -531,9 +519,10 @@ class Assembler : public AssemblerBase { // This is for calls and branches within generated code. The serializer // has already deserialized the lui/ori instructions etc. inline static void deserialization_set_special_target_at( - Address instruction_payload, Address target) { + Address instruction_payload, Code* code, Address target) { set_target_address_at( instruction_payload - kInstructionsFor32BitConstant * kInstrSize, + code, target); } @@ -657,7 +646,7 @@ class Assembler : public AssemblerBase { void jal_or_jalr(int32_t target, Register rs); - //-------Data-processing-instructions--------- + // -------Data-processing-instructions--------- // Arithmetic. void addu(Register rd, Register rs, Register rt); @@ -695,7 +684,7 @@ class Assembler : public AssemblerBase { void rotrv(Register rd, Register rt, Register rs); - //------------Memory-instructions------------- + // ------------Memory-instructions------------- void lb(Register rd, const MemOperand& rs); void lbu(Register rd, const MemOperand& rs); @@ -711,7 +700,12 @@ class Assembler : public AssemblerBase { void swr(Register rd, const MemOperand& rs); - //-------------Misc-instructions-------------- + // ----------------Prefetch-------------------- + + void pref(int32_t hint, const MemOperand& rs); + + + // -------------Misc-instructions-------------- // Break / Trap instructions. void break_(uint32_t code, bool break_as_stop = false); @@ -744,7 +738,7 @@ class Assembler : public AssemblerBase { void ins_(Register rt, Register rs, uint16_t pos, uint16_t size); void ext_(Register rt, Register rs, uint16_t pos, uint16_t size); - //--------Coprocessor-instructions---------------- + // --------Coprocessor-instructions---------------- // Load, store, and move. void lwc1(FPURegister fd, const MemOperand& src); @@ -850,10 +844,10 @@ class Assembler : public AssemblerBase { assem_->EndBlockGrowBuffer(); } - private: - Assembler* assem_; + private: + Assembler* assem_; - DISALLOW_IMPLICIT_CONSTRUCTORS(BlockGrowBufferScope); + DISALLOW_IMPLICIT_CONSTRUCTORS(BlockGrowBufferScope); }; // Debugging. @@ -971,6 +965,12 @@ class Assembler : public AssemblerBase { void CheckTrampolinePool(); + // Allocate a constant pool of the correct size for the generated code. + Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate); + + // Generate the constant pool for the generated code. + void PopulateConstantPool(ConstantPoolArray* constant_pool); + protected: // Relocation for a type-recording IC has the AST id added to it. This // member variable is a way to pass the information from the call site to |