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| author | Paul Kirth <paulkirth@google.com> | 2024-05-09 17:21:33 -0700 |
|---|---|---|
| committer | Paul Kirth <paulkirth@google.com> | 2024-05-09 17:21:33 -0700 |
| commit | 0a3874226b4dbef5e695e10e96564a39bfba08fd (patch) | |
| tree | dc8c7b76cdbaa16ac2078c6d196f29e53fc988e0 | |
| parent | 2e1b3c861fbefe3f08d224527bb650f49670d1e4 (diff) | |
[𝘀𝗽𝗿] changes introduced through rebaseupstream/users/ilovepi/spr/main.reapply-llvmriscv-enable-trailing-fences-for-seq-cst-stores-by-default-87376
Created using spr 1.3.4
[skip ci]
| -rw-r--r-- | llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/attributes.ll | 4 |
3 files changed, 7 insertions, 3 deletions
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp index 6f5f12cc7286..45ca0f4b57dd 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp @@ -76,7 +76,8 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI, emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString()); } - if (STI.hasFeature(RISCV::FeatureStdExtA)) { + if (STI.hasFeature(RISCV::FeatureAbiAttributes) && + STI.hasFeature(RISCV::FeatureStdExtA)) { unsigned AtomicABITag = STI.hasFeature(RISCV::FeatureTrailingSeqCstFence) ? RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6S : RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6C; diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index c3dc4ea53697..c1d0d01082d0 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1221,6 +1221,9 @@ def FeatureTrailingSeqCstFence : SubtargetFeature<"seq-cst-trailing-fence", "true", "Enable trailing fence for seq-cst store.">; +def FeatureAbiAttributes : SubtargetFeature<"abi-attr", "EnableAbiAttributes", + "true", "Enable emitting RISC-V ABI attributes">; + def FeatureUnalignedScalarMem : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem", "true", "Has reasonably performant unaligned scalar " diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 1aff3e8b83f4..272659d8d2eb 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -129,8 +129,8 @@ ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64ZMMUL %s ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s -; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6C %s -; RUN: llc -mtriple=riscv64 -mattr=+a,+seq-cst-trailing-fence %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6S %s +; RUN: llc -mtriple=riscv64 -mattr=+a,+abi-attr %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6C %s +; RUN: llc -mtriple=riscv64 -mattr=+a,+seq-cst-trailing-fence,+abi-attr %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6S %s ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV64C %s |