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* [𝘀𝗽𝗿] initial versionupstream/users/MaskRay/spr/riscv-restore-dw_eh_pe_uleb128-call-site-encoding-for-gcc_except_tableFangrui Song2024-01-072-10/+7
| | | | Created using spr 1.3.4
* [ELF] Improve OVERLAY testsFangrui Song2024-01-073-50/+80
| | | | | | | | | | | Also test two issues: * When the start address is `.`, subsequent sections don't share the address of the first overlay section. * When the first overlay section is empty and discardable, `p_paddr` is incorrectly zero. This is because a discarded section has a zero address, causing `prev->getLMA() + prev->size` where `prev` refers to the first section to evaluate to zero.
* [gn] port 92e243173c09Nico Weber2024-01-071-0/+1
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* [GlobalISel][NFC]Delete the comments of XXLegalizerInfo (#76918)Ningning Shi(史宁宁)2024-01-086-6/+0
| | | | Delete the LegalizerInfo comments of AArch64/AMD64/ARM/M68k/RISCV/x86, they are copied from register bank.
* Revert "[CMake] Include riscv32-unknown-elf runtimes in Fuchsia toolchain ↵Petr Hosek2024-01-081-37/+1
| | | | | | | (#76849)" This reverts commit 78550bef98347bccbf0e8e5fb66dc59718fc35ec since it broke the two stage build.
* [RISCV][NFC] Move Zawrs/Zacas implementation to RISCVInstrInfoZa.td (#76940)Wang Pengcheng2024-01-083-27/+46
| | | | | To keep the structure of TableGen files clear. The definitions are simplified by the way.
* [PowerPC] Precommit test for lowering llvm.trap on ppc64le. NFC.Kai Luo2024-01-081-0/+10
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* [CMake] Include riscv32-unknown-elf runtimes in Fuchsia toolchain (#76849)Petr Hosek2024-01-071-1/+37
| | | | | This contains compiler-rt builtins and llvm-libc for baremetal use. Differential Revision: https://reviews.llvm.org/D155337
* [Sema] Warning for _Float16 passed to format specifier '%f' (#74439)Haocong Lu2024-01-084-7/+18
| | | | | | | | | | According to https://www.open-std.org/jtc1/sc22/wg14/www/docs/n2844.pdf, default argument promotions for _FloatN types has been removed. A warning is needed to notice user to promote _Float16 to double explicitly, and then pass it to format specifier '%f', which is consistent with GCC. Fixes: https://github.com/llvm/llvm-project/issues/68538
* [PowerPC] make LR/LR8 CTR/CTR8 aliased (#76926)Chen Zheng2024-01-082-7/+14
| | | | fixes https://github.com/llvm/llvm-project/issues/47156 fixes https://github.com/llvm/llvm-project/issues/47155
* [NFC] Remove trailing whitespace in `llvm/lib/Target/AMDGPU/VOP2Instructions.td`Shilei Tian2024-01-071-1/+1
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* [InstrProfiling] No runtime registration for ELF, COFF, Mach-O and XCOFF ↵Petr Hosek2024-01-073-16/+16
| | | | | | | | | (#77225) Whether runtime registration is needed is not dependent on the OS but the file format. For ELF, COFF, Mach-O or XCOFF, we can always use the linker support. This is important for baremetal platforms such as RTOS and UEFI platforms where there is no OS but we still don't want to use runtime registration and rely on linker support instead.
* [ELF,test] Add eh-frame-nonzero-offset-riscv.s for #65966Fangrui Song2024-01-071-0/+53
| | | | | | I plan to define RISCV::relocateAllocate in a subsequent change. Add a test to verify `else if (auto *ehIn = dyn_cast<EhInputSection>(&sec)) secAddr += ehIn->getParent()->outSecOff;`
* [NFC][ObjectSize] Make method publicBill Wendling2024-01-071-17/+11
| | | | | Windows barfs on the 'friend class SizeOffsetType;' statement. Attempt to fix by making the method called by the "friend" class public.
* [clang] [MinGW] Don't look for a GCC in path if the install base has a ↵Martin Storsjö2024-01-072-2/+51
| | | | | | | | | | | | | | | proper mingw sysroot (#76949) This fixes uses of the MSYS2 clang64 environment compilers, if another set of GCC based compilers are available further back in PATH (which may be explicitly added, or inherited unintentionally from other software installed). (The issue in the clang64 environment can be worked around somewhat by installing *-gcc-compat packages which present aliases named <triple>-gcc within the clang64 environment as well.) This fixes https://github.com/msys2/MINGW-packages/issues/11495 and https://github.com/msys2/MINGW-packages/issues/19279.
* [RISCV] Merge machine operand flag MO_PLT into MO_CALL (#77253)Fangrui Song2024-01-0737-283/+267
| | | | | | | | | | | | | | | | | Since #72467, `@plt` in assembly output "call foo@plt" is omitted. We can trivially merge MO_PLT and MO_CALL without any functional change to assembly/relocatable file output. Earlier architectures use different call relocation types whether a PLT is potentially needed: R_386_PLT32/R_386_PC32, R_68K_PLT32/R_68K_PC32, R_SPARC_WDISP30/R_SPARC_WPLT320. However, as the PLT property is per-symbol instead of per-call-site and linkers can optimize out a PLT, the distinction has been confusing. Arm made good names R_ARM_CALL/R_AARCH64_CALL. Let's use MO_CALL instead of MO_PLT. As follow-ups, we can merge fixup_riscv_call/fixup_riscv_call_plt and VK_RISCV_CALL/VK_RISCV_CALL_PLT.
* [RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)Fangrui Song2024-01-07205-6584/+6581
| | | | | | | | | | | | | R_RISCV_CALL/R_RISCV_CALL_PLT distinction is not necessary and R_RISCV_CALL has been deprecated. Since https://reviews.llvm.org/D132530 `call foo` assembles to R_RISCV_CALL_PLT. The `@plt` suffix is not useful and can be removed now (matching AArch64 and PowerPC). GNU assembler assembles `call foo` to RISCV_CALL_PLT since 2022-09 (70f35d72ef04cd23771875c1661c9975044a749c). Without this patch, unconditionally changing MO_CALL to MO_PLT could create `jump .L1@plt, a0`, which is invalid in LLVM integrated assembler and GNU assembler.
* [lld][ELF][X86] Add missing X86_64_TPOFF64 case in switches (#77208)Nicholas Mosier2024-01-072-3/+17
| | | | | | Close #77201. When linking code with a R_X86_64_TPOFF64 relocation, LLD exits with an 'unknown reloaction' error message due to two missing cases in relocation switch statements. This patch adds in those cases so that LLD successfully links code R_X86_64_TPOFF64 relocations.
* [libc] Attempt to fix incorrect pathin on Linux buildsJoseph Huber2024-01-071-2/+2
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* [libc] Fix GPU tests not running after recent patches (#77248)Joseph Huber2024-01-073-41/+54
| | | | | | | | | | | | | | | Summary: A previous patch added a dependency on the stack protectors, this was not built on the GPU targets so every test was disabled. It turns out that disabled tests still get targets so we need to specifically check if the it is in the target's set of entrypoints before we can use it. Another patch, because the build-bot was down, snuck in that prevented the new math tests from being run. The problem is that the `signal.h` header requires target specific definitions but was being used unconditionally. I have made changes that disable building this header if the file is not defined in the config. This required disbaling the signal_to_string utility, so that will simply be missing from targets that don't define it.
* Reapply "[libc++][streams] P1759R6: Native handles and file streams" (#77190)Hristo Hristov2024-01-0725-30/+523
| | | | | | | | | | | Fixes build on Windows in C++26 mode. Reverted in: https://github.com/llvm/llvm-project/commit/40c07b559aa6ab4bac074c943967d3207bc07ae0 Original PR: https://github.com/llvm/llvm-project/pull/76632 --------- Co-authored-by: Zingam <zingam@outlook.com>
* NFC: Extract switch lowering binary tree splitting code from DAG into ↵Amara Emerson2024-01-074-84/+99
| | | | | | | SwitchLoweringUtils. This will help re-use this code with the upcoming GlobalISel implementation of this optimization.
* [PatternMatch] Fix typo in comment (NFC) (#77240)natanelh-mobileye2024-01-071-1/+1
| | | | Tiny spelling mistake fixup. please review the two lines of code below to see the correctness of this PR.
* [OpenMP][Obvious] Fix test failing on BE architecturesJoseph Huber2024-01-071-1/+1
| | | | | | Summary: This accidentally included a byte past the magic, which was out of order on big endian architectures.
* [libc++][doc] Minor release notes style fixes.Mark de Wever2024-01-071-3/+2
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* [NFC][libc++] Formats tuple.Mark de Wever2024-01-071-14/+18
| | | | | The fix used macros that confuses clang-format. This is formatted with clang-format and then excluded from formatting.
* [VPlan] Manage InBounds via VPRecipeWithIRFlags for VectorPtrRecipe.Florian Hahn2024-01-075-26/+42
| | | | | | | | | As suggested as follow-up in https://github.com/llvm/llvm-project/pull/72164, manage inbounds via VPRecipeWithIRFlags. Note that in some cases we can now preserve inbounds in a few more cases.
* [LV] Add test showing overly aggressive dropping of inbounds.Florian Hahn2024-01-071-0/+50
| | | | | | | As %B.gep.0 executes unconditionally in the latch, inbounds could be preserved in the vector version. https://alive2.llvm.org/ce/z/XWbMuD
* [libc++][test] Improves suspurious clang diagnostics. (#77234)Mark de Wever2024-01-072-32/+22
| | | | | | As suggested by @philnik777 this is a better fix than 02a33b72fd21cdbf476d6bda72faa462e073e510 Fixes: https://github.com/llvm/llvm-project/issues/77123
* [mlir][IR] `DominanceInfo`: Add function to query dominator of a range of ↵Matthias Springer2024-01-072-22/+40
| | | | | | | block (#77098) Also improve the implementation of `findCommonDominator` (skip duplicate blocks) and extract it from `BufferPlacementTransformationBase` (so that `BufferPlacementTransformationBase` can be retired eventually).
* [mlir][Interfaces][NFC] Move region loop detection to ↵Matthias Springer2024-01-075-65/+66
| | | | | | | | | | | | | | | | | `RegionBranchOpInterface` (#77090) `BufferPlacementTransformationBase::isLoop` checks if there a loop in the region branching graph of an operation. This algorithm is similar to `isRegionReachable` in the `RegionBranchOpInterface`. To avoid duplicate code, `isRegionReachable` is generalized, so that it can be used to detect region loops. A helper function `RegionBranchOpInterface::hasLoop` is added. This change also turns a recursive implementation into an iterative one, which is the preferred implementation strategy in LLVM. Also move the `isLoop` to `BufferOptimizations.cpp`, so that we can gradually retire `BufferPlacementTransformationBase`. (This is so that proper error handling can be added to `BufferViewFlowAnalysis`.)
* [InstCombine] Relax the one-use constraints for `icmp pred (binop X, Z), ↵Yingwei Zheng2024-01-072-2/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (binop Y, Z)` (#76384) This patch relaxes the one-use constraints for `icmp pred (binop X, Z), (binop Y, Z)`. It will enable more optimizations with pointer arithmetic. One example in `boost::match_results::set_size`: ``` declare void @use(i64) define i1 @src(ptr %a1, ptr %a2, ptr %add.ptr.i66, i64 %sub.ptr.rhs.cast.i) { %sub.ptr.lhs.cast.i = ptrtoint ptr %a1 to i64 %sub.ptr.rhs.cast.i = ptrtoint ptr %a2 to i64 %sub.ptr.sub.i = sub i64 %sub.ptr.lhs.cast.i, %sub.ptr.rhs.cast.i %sub.ptr.div.i = sdiv exact i64 %sub.ptr.sub.i, 24 call void @use(i64 %sub.ptr.div.i) %sub.ptr.lhs.cast.i.i = ptrtoint ptr %add.ptr.i66 to i64 %sub.ptr.sub.i.i = sub i64 %sub.ptr.lhs.cast.i.i, %sub.ptr.rhs.cast.i %sub.ptr.div.i.i = sdiv exact i64 %sub.ptr.sub.i.i, 24 %cmp.i.not.i.i = icmp eq i64 %sub.ptr.div.i.i, %sub.ptr.div.i ret i1 %cmp.i.not.i.i } define i1 @tgt(ptr %a1, ptr %a2, ptr %add.ptr.i66, i64 %sub.ptr.rhs.cast.i) { %sub.ptr.lhs.cast.i = ptrtoint ptr %a1 to i64 %sub.ptr.rhs.cast.i = ptrtoint ptr %a2 to i64 %sub.ptr.sub.i = sub i64 %sub.ptr.lhs.cast.i, %sub.ptr.rhs.cast.i %sub.ptr.div.i = sdiv exact i64 %sub.ptr.sub.i, 24 call void @use(i64 %sub.ptr.div.i) %cmp.i.not.i.i = icmp eq i64 %sub.ptr.sub.i.i, %sub.ptr.sub.i ret i1 %cmp.i.not.i.i } ```
* Revert "[NFC][ObjectSizeOffset] Add template stuff for Visual Studio"Bill Wendling2024-01-071-3/+3
| | | | | | This reverts commit 0903d992cc961281a0bffc8704796f27f8c2e696. This is causing all non-Visual Studio builds fail.
* [NFC][ObjectSizeOffset] Add template stuff for Visual StudioBill Wendling2024-01-071-3/+3
| | | | | | | Visual Studio needs the class template stuff. C:\llvm\include\llvm/Analysis/MemoryBuiltins.h(217): error C2990: 'llvm::SizeOffsetType': non-class template has already been declared as a class template C:\llvm\include\llvm/Analysis/MemoryBuiltins.h(193): note: see declaration of 'llvm::SizeOffsetType'
* [MLIR][Presburger] Implement IntegerRelation::mergeAndAlignSymbols (#76736)Bharathi Ramana Joshi2024-01-073-0/+283
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* [MLIR][Presburger] Fix ParamPoint to be column-wise instead of row-wise (#77232)Abhinav2718282024-01-072-10/+10
| | | | The ParamPoint datatype has each column representing an affine function. The code for generating functions is modified to reflect this.
* [MLIR][Presburger] Definitions for basic functions related to cones (#76650)Abhinav2718282024-01-075-0/+199
| | | | | We add some basic type aliases and function definitions relating to cones for Barvinok's algorithm. These include functions to get the dual of a cone and find its index.
* [Clang][NFC] Fix trailing whitespace in ReleaseNotes.rstcor3ntin2024-01-071-1/+1
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* [AArch64] Fix condition for combining UADDV and Add. (#76809)David Green2024-01-072-2/+70
| | | | | | | This should have been checking that the transform was valid, but used incorrect conditions letting through invalid combinations of lo/hi extracts. Hopefully fixes #76769
* [RISCV] Don't attempt PRE if available info is SEW/LMUL ratio only (#77063)Luke Lau2024-01-072-0/+62
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* [asan,test] Improve tests to ensure instrumentation even in the presence of ↵Fangrui Song2024-01-063-28/+40
| | | | StackSafetyAnalysis
* [mlir][spirv] Use assemblyFormat to define atomic op assembly (#76323)Alex Beloi2024-01-0611-517/+192
| | | | | | | | | | | | | | | | see #73359 Declarative assemblyFormat ODS is more concise and requires less boilerplate than filling out CPP interfaces. Changes: * updates the Ops defined in `SPIRVAtomicOps.td` to use assemblyFormat. * Removes print/parse from`AtomcOps.cpp` which is now generated by assemblyFormat * Adds `Trait` to verify that a pointer operand `foo`'s pointee type matches operand `bar`'s type * * Updates error message expected in tests from new Trait * Updates tests to updated format (largely using <operand> in place of "operand")
* Revert "[RISCV] Refactor subreg indices. (#77173)"Craig Topper2024-01-064-26/+20
| | | | | | | This reverts commit b5de136ef3fd63c6a6aabaea16792e47be1eeeff. Based on post commit feedback, I need to some other work before this makes sense.
* [test] Test StackSafetyAnalysis handles MemIntrinsic even in the presence of ↵Fangrui Song2024-01-061-0/+18
| | | | __asan_memcpy
* [docs] Small spelling fix ("if <...>`than` -> if <...> `then`") (#77215)Mircea Trofin2024-01-061-1/+1
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* [mlir][python] add MemRefTypeAttr attr builder (#76371)Maksim Levental2024-01-062-0/+17
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* [gn build] Manually port ba3ef331Arthur Eubanks2024-01-062-6/+6
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* [mlir][spirv] Support alias/restrict function argument decorations (#76353)Kohei Yamaguchi2024-01-0614-71/+390
| | | | | | | Closes #76106 --------- Co-authored-by: Lei Zhang <antiagainst@gmail.com>
* [RISCV] Refactor subreg indices. (#77173)Craig Topper2024-01-064-20/+26
| | | | | | | | | -Rename sub_32_hi to sub_gpr_odd -Add dedicated sub_gpr_even. -Rename sub_32 and sub_16 to sub_fpr32 and sub_fpr16. -Remove start offset from sub_gpr_odd. AArch64 doesn't use non-zero offset for GPR tuples so I don't think we need to. This is preparation for a RV64 GPRPair for Zacas.
* Revert "[GlobalIsel] Combine select of binops (#76763)"Thorsten Schütt2024-01-064-322/+28
| | | | This reverts commit 1687555572ee4fb435da400dde02e7a1e60b742c.
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