Fix typoupstream/users/wangpc-pp/spr/riscv-remove-sew-operand-for-loadstore-and-sew-aware-pseudos

Created using spr 1.3.6-beta.1

1 files changed, 3 insertions, 3 deletions

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index cb5ab1e3a429..0f2075cb29a0 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -180,8 +180,8 @@ static inline bool hasRoundModeOp(uint64_t TSFlags) {
 /// \returns true if this instruction uses vxrm
 static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
 
-/// \returns true if this instruction has implict SEW value.
-static inline bool hasImplictSEW(uint64_t TSFlags) {
+/// \returns true if this instruction has implicit SEW value.
+static inline bool hasImplicitSEW(uint64_t TSFlags) {
   return TSFlags & HasImplictSEWMask;
 }
 
@@ -192,7 +192,7 @@ static inline VSEW getVSEW(uint64_t TSFlags) {
 
 /// \returns true if there is a SEW value for the instruction.
 static inline bool hasSEW(uint64_t TSFlags) {
-  return hasSEWOp(TSFlags) || hasImplictSEW(TSFlags);
+  return hasSEWOp(TSFlags) || hasImplicitSEW(TSFlags);
 }
 
 static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {