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Diffstat (limited to 'examples/baremetal/stm32f4discovery/blueblink/system.h')
| -rw-r--r-- | examples/baremetal/stm32f4discovery/blueblink/system.h | 129 |
1 files changed, 129 insertions, 0 deletions
diff --git a/examples/baremetal/stm32f4discovery/blueblink/system.h b/examples/baremetal/stm32f4discovery/blueblink/system.h new file mode 100644 index 000000000..6e7190026 --- /dev/null +++ b/examples/baremetal/stm32f4discovery/blueblink/system.h @@ -0,0 +1,129 @@ +/**************************************************************************** +** +** Copyright (C) 2019 Denis Shienkov <denis.shienkov@gmail.com> +** Contact: https://www.qt.io/licensing/ +** +** This file is part of the examples of Qbs. +** +** $QT_BEGIN_LICENSE:BSD$ +** Commercial License Usage +** Licensees holding valid commercial Qt licenses may use this file in +** accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The Qt Company. For licensing terms +** and conditions see https://www.qt.io/terms-conditions. For further +** information use the contact form at https://www.qt.io/contact-us. +** +** BSD License Usage +** Alternatively, you may use this file under the terms of the BSD license +** as follows: +** +** "Redistribution and use in source and binary forms, with or without +** modification, are permitted provided that the following conditions are +** met: +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in +** the documentation and/or other materials provided with the +** distribution. +** * Neither the name of The Qt Company Ltd nor the names of its +** contributors may be used to endorse or promote products derived +** from this software without specific prior written permission. +** +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +** "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +** LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +** A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +** OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +** SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE." +** +** $QT_END_LICENSE$ +** +****************************************************************************/ + +#ifndef SYSTEM_H +#define SYSTEM_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#define __IO volatile + +// General purpose input/output registers map. +struct gpio_regs_map { + __IO uint32_t MODER; + __IO uint32_t OTYPER; + __IO uint32_t OSPEEDR; + __IO uint32_t PUPDR; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t LCKR; + __IO uint32_t AFR[2u]; +}; + +// Reset and clock control registers map. +struct rcc_regs_map { + __IO uint32_t CR; + __IO uint32_t PLLCFGR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t AHB1RSTR; + __IO uint32_t AHB2RSTR; + __IO uint32_t AHB3RSTR; + uint32_t RESERVED0; + __IO uint32_t APB1RSTR; + __IO uint32_t APB2RSTR; + uint32_t RESERVED1[2u]; + __IO uint32_t AHB1ENR; + __IO uint32_t AHB2ENR; + __IO uint32_t AHB3ENR; + uint32_t RESERVED2; + __IO uint32_t APB1ENR; + __IO uint32_t APB2ENR; + uint32_t RESERVED3[2u]; + __IO uint32_t AHB1LPENR; + __IO uint32_t AHB2LPENR; + __IO uint32_t AHB3LPENR; + uint32_t RESERVED4; + __IO uint32_t APB1LPENR; + __IO uint32_t APB2LPENR; + uint32_t RESERVED5[2u]; + __IO uint32_t BDCR; + __IO uint32_t CSR; + uint32_t RESERVED6[2u]; + __IO uint32_t SSCGR; + __IO uint32_t PLLI2SCFGR; +}; + +#define PERIPH_ADDRESS (0x40000000u) + +#define APB2PERIPH_ADDRESS (PERIPH_ADDRESS + 0x00010000u) +#define AHB1PERIPH_ADDRESS (PERIPH_ADDRESS + 0x00020000u) + +// APB2 peripherals. +#define SYSCFG_REGS_ADDRESS (APB2PERIPH_ADDRESS + 0x3800u) +#define EXTI_REGS_ADDRESS (APB2PERIPH_ADDRESS + 0x3C00u) + +// AHB1 peripherals. +#define GPIOD_REGS_ADDRESS (AHB1PERIPH_ADDRESS + 0x0C00u) +#define RCC_REGS_ADDRESS (AHB1PERIPH_ADDRESS + 0x3800u) + +#define GPIOD_REGS_MAP ((struct gpio_regs_map *)GPIOD_REGS_ADDRESS) +#define RCC_REGS_MAP ((struct rcc_regs_map *)RCC_REGS_ADDRESS) + +#ifdef __cplusplus +} +#endif + +#endif // SYSTEM_H |