Port the ARM atomics to the new QBasicAtomicXXX architecture

The implementation is divided in two files, as it used to be in the
previous implementation: one for ARMv5, one for ARMv6 and up.

For the ARMv5 implementation:

    Drop the non-Linux EABI version of the atomics, as it's not
    ABI-compatible with the ARMv6 and ARMv7 implementations. This
    means this ARMv5 implementation only works on Linux. If other
    systems implement kernel helpers like Linux, they can be added
    too.

    We use the __kernel_cmpxchg located at 0xffff0fc0 to implement the
    operations, except for fetchAndStore, for which we use the SWP
    instruction.

    Also introduce the use of __kernel_dmb (at 0xffff0fa0) for the
    memory barrier. Now this code is SMP-safe even when built with
    ARMv5.

    The kernel cmpxchg helper was introduced in Linux 2.6.12, whereas
    the dmb helper was introduced in 2.6.15. That means 2.6.15 is the
    minimum version now.

For ARMv6 and up:

    Introduce byte, half-word and doubleword atomics that work on
    ARMv6K and up.

    For ARMv6 specifically, the memory barrier instruction (DMB) isn't
    present, so we need to accomplish the same with the MCR
    coprocessor instruction.

Change-Id: Ife7f9b920bcc7d1eef7611761f6c59ea940ec7df
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>

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