diff options
author | Thiago Macieira <thiago.macieira@intel.com> | 2012-01-24 13:49:26 -0200 |
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committer | Qt by Nokia <qt-info@nokia.com> | 2012-03-24 15:10:00 +0100 |
commit | acc97163316133f88dc06f39239776b025dbe34e (patch) | |
tree | b86202eb47b6a1c725bd7373cb21434068025b9a /src/corelib/arch | |
parent | 1ba5796d0903afed48f2ca179e75786c1786c707 (diff) |
Add the missing 'itt eq' instructions to the ARM atomics.
This affected the 16- and 64-bit sizes only. Must have been a C&P failure.
Change-Id: If7b1e534a61d812226a6e4970909b53b0cc5a9a6
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
Diffstat (limited to 'src/corelib/arch')
-rw-r--r-- | src/corelib/arch/qatomic_armv6.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/corelib/arch/qatomic_armv6.h b/src/corelib/arch/qatomic_armv6.h index 41f145ad0d..b290a6a008 100644 --- a/src/corelib/arch/qatomic_armv6.h +++ b/src/corelib/arch/qatomic_armv6.h @@ -387,6 +387,7 @@ bool QBasicAtomicOps<2>::testAndSetRelaxed(T &_q_value, T expectedValue, T newVa asm volatile("0:\n" "ldrexh %[result], [%[_q_value]]\n" "eors %[result], %[result], %[expectedValue]\n" + "itt eq\n" "strexheq %[result], %[newValue], [%[_q_value]]\n" "teqeq %[result], #1\n" "beq 0b\n" @@ -497,6 +498,7 @@ bool QBasicAtomicOps<8>::testAndSetRelaxed(T &_q_value, T expectedValue, T newVa "eor %[result], %[result], %[expectedValue]\n" "eor %H[result], %H[result], %H[expectedValue]\n" "orrs %[result], %[result], %H[result]\n" + "itt eq\n" "strexdeq %[result], %[newValue], %H[newValue], [%[_q_value]]\n" "teqeq %[result], #1\n" "beq 0b\n" |