CMake: update the x86 intrinsic checks

Merge all the existing checks into a single one, which is a simple pass
or fail, since all our supported compilers support all the intrinsics up
to Cannon Lake. The two I've recently added (AVX512VBMI2 and VAES)
aren't yet supported everywhere, so they stay.

For some reason, all intrinsics seem to be disabled on Android. It looks
like some support was missing during the CMake port and this was never
again looked at. I'm leaving it be.

As for WASM, discussion with maintainers is that the WASM emulation of
x86 intrinsics is too hit-and-miss. No one is testing the performance,
particularly the person writing such code (me). They also have some
non-obvious selection of what is supported natively and what is
merely emulated. Using the actual WASM intrinsics is preferred, but
someone else's job.

Change-Id: Ib42b3adc93bf4d43bd55fffd16c10d66208e8384
Reviewed-by: Tor Arne Vestbø <tor.arne.vestbo@qt.io>
Reviewed-by: Morten Johan Sørvig <morten.sorvig@qt.io>
Reviewed-by: Lorn Potter <lorn.potter@gmail.com>
Reviewed-by: Kai Koehne <kai.koehne@qt.io>

1 files changed, 37 insertions, 27 deletions

diff --git a/src/corelib/global/qsimd_p.h b/src/corelib/global/qsimd_p.h
index 5df2faf4e4..af557bc976 100644
--- a/src/corelib/global/qsimd_p.h
+++ b/src/corelib/global/qsimd_p.h
@@ -34,33 +34,6 @@ QT_WARNING_DISABLE_INTEL(103)
     for (int _i = 0; _i < max && i < length; ++i, ++_i)
 
 /*
- * qt_module_config.prf defines the QT_COMPILER_SUPPORTS_XXX macros.
- * They mean the compiler supports the necessary flags and the headers
- * for the x86 and ARM intrinsics:
- *  - GCC: the -mXXX or march=YYY flag is necessary before #include
- *    up to 4.8; GCC >= 4.9 can include unconditionally
- *  - Intel CC: #include can happen unconditionally
- *  - MSVC: #include can happen unconditionally
- *  - RVCT: ???
- *
- * We will try to include all headers possible under this configuration.
- *
- * MSVC does not define __SSE2__ & family, so we will define them. MSVC 2013 &
- * up do define __AVX__ if the -arch:AVX option is passed on the command-line.
- *
- * Supported XXX are:
- *   Flag    | Arch |  GCC  | Intel CC |  MSVC  |
- *  ARM_NEON | ARM  | I & C | None     |   ?    |
- *  SSE2     | x86  | I & C | I & C    | I & C  |
- *  SSE3     | x86  | I & C | I & C    | I only |
- *  SSSE3    | x86  | I & C | I & C    | I only |
- *  SSE4_1   | x86  | I & C | I & C    | I only |
- *  SSE4_2   | x86  | I & C | I & C    | I only |
- *  AVX      | x86  | I & C | I & C    | I & C  |
- *  AVX2     | x86  | I & C | I & C    | I only |
- *  AVX512xx | x86  | I & C | I & C    | I only |
- * I = intrinsics; C = code generation
- *
  * Code can use the following constructs to determine compiler support & status:
  * - #ifdef __XXX__      (e.g: #ifdef __AVX__  or #ifdef __ARM_NEON__)
  *   If this test passes, then the compiler is already generating code for that
@@ -160,6 +133,43 @@ QT_WARNING_DISABLE_INTEL(103)
 #  define QT_FUNCTION_TARGET(x)
 #endif
 
+#if defined(__SSE2__) && !defined(QT_COMPILER_SUPPORTS_SSE2) && !defined(QT_BOOTSTRAPPED)
+// Intrinsic support appears to be missing, so pretend these features don't exist
+#  undef __SSE__
+#  undef __SSE2__
+#  undef __SSE3__
+#  undef __SSSE3__
+#  undef __SSE4_1__
+#  undef __SSE4_2__
+#  undef __AES__
+#  undef __POPCNT__
+#  undef __AVX__
+#  undef __F16C__
+#  undef __RDRND__
+#  undef __AVX2__
+#  undef __BMI__
+#  undef __BMI2__
+#  undef __FMA__
+#  undef __MOVBE__
+#  undef __RDSEED__
+#  undef __AVX512F__
+#  undef __AVX512ER__
+#  undef __AVX512CD__
+#  undef __AVX512PF__
+#  undef __AVX512DQ__
+#  undef __AVX512BW__
+#  undef __AVX512VL__
+#  undef __AVX512IFMA__
+#  undef __AVX512VBMI__
+#  undef __SHA__
+#  undef __AVX512VBMI2__
+#  undef __AVX512BITALG__
+#  undef __AVX512VNNI__
+#  undef __AVX512VPOPCNTDQ__
+#  undef __GFNI__
+#  undef __VAES__
+#endif
+
 #ifdef Q_PROCESSOR_X86
 /* -- x86 intrinsic support -- */