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* Merge "Merge remote-tracking branch 'origin/stable' into dev" into ↵Frederik Gladhorn2013-01-2321-21/+21
|\ | | | | | | refs/staging/dev
| * Update copyright year in Digia's license headersSergio Ahumada2013-01-1821-21/+21
| | | | | | | | | | Change-Id: Ic804938fc352291d011800d21e549c10acac66fb Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* | VxWorks process (RTP) mode does not have taskLock/taskUnlock functionsPasi Petäjäjärvi2013-01-231-0/+5
|/ | | | | | | | | VxWorks does not support to globally lock and unlock the scheduler from process. In kernel mode (DKM) above functions disable preemption from requested task and such functionality does not exist for process. Change-Id: Id41eab4c1973e4181e82539d08707659e0780f99 Reviewed-by: Samuel Rødal <samuel.rodal@digia.com>
* Change copyrights from Nokia to DigiaIikka Eklund2012-09-2223-550/+550
| | | | | | | | Change copyrights and license headers from Nokia to Digia Change-Id: If1cc974286d29fd01ec6c19dd4719a67f4c3f00e Reviewed-by: Lars Knoll <lars.knoll@digia.com> Reviewed-by: Sergio Ahumada <sergio.ahumada@digia.com>
* Enable QAtomicInteger for char16_t and char32_tThiago Macieira2012-08-187-0/+47
| | | | | | | | | | | Those are regular, integer types, of 16- and 32-bit width, respectively. C++11's std::atomic supports them, so we should too. C++11 also supports wchar_t, but since that type's size can change, I don't feel like support for it in Qt is pressing. Change-Id: I945b641c91a8a98be82715f878c382dee58ac98b Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
* Add Q_DECL_CONSTEXPR to the isXXX functions in the new atomics.Thiago Macieira2012-08-189-60/+60
| | | | | | | | | This allows one to write code that depends on these values at compile-time. Change-Id: I7d78524ed9c70d4141360496d1d764dcbfa92e62 Reviewed-by: Marc Mutz <marc.mutz@kdab.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Mark all atomic functions as Q_DECL_NOTHROWThiago Macieira2012-08-0911-284/+284
| | | | | | | | | | | | | | | | | | | | | | | | | Actually, only the "new" atomics are marked. The old implementation, based on qoldbasicatomic.h is unchanged, but should still work without a problem. The following configurations were tested and do work: - x86 64-bit - x86 32-bit - generic GCC - generic C++11 std::atomic - bootstrap - ARMv6 and 7 - MIPS - MSVC 2010 32-bit - MSVC 2010 64-bit The only two configurations untested are IA-64 and ARMv5. Except for MSVC, all configurations were tested with GCC 4.6 (MIPS and ARM) and 4.7 (x86 and generics). Change-Id: Iecbfeacd9d20b535453e91335165e9a221e0b47e Reviewed-by: Marc Mutz <marc.mutz@kdab.com> Reviewed-by: Lars Knoll <lars.knoll@nokia.com>
* Add a T parameter to the memory barrier functions in atomics.Thiago Macieira2012-08-075-25/+27
| | | | | | | | This is so we can insert valgrind (helgrind) annotation macros. They require the actual address of the variable to work. Change-Id: I988f6a46385ad58143c53ad34b6cf0f58be2cdb8 Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
* Fix some spelling errorsSergio Ahumada2012-07-111-1/+1
| | | | | | Change-Id: I19d3b2e9a5180b13deb828b55195404ef20be295 Reviewed-by: Daniel Teske <daniel.teske@nokia.com> Reviewed-by: Giuseppe D'Angelo <giuseppe.dangelo@kdab.com>
* Compile with -qtnamespace on WindowsBradley T. Hughes2012-05-101-11/+11
| | | | | | | | qatomic_msvc.h declares some Windows intrinsic functions which should not be in the Qt namespace. Change-Id: I1b2f91798159c08cf167ee3d1ed2818c12c9b833 Reviewed-by: Friedemann Kleint <Friedemann.Kleint@nokia.com>
* Fix atomics on SPARCThiago Macieira2012-04-251-8/+8
| | | | | | | | | Inspired by https://bugreports.qt-project.org/secure/attachment/26020/qt_atomic_sparc64.patch Task-number: QTBUG-22479 Change-Id: Ie3275df96c639d6a75e05f70fe5745aeb34457f9 Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
* Unify the atomic implementation for x86 architecturesThiago Macieira2012-03-283-392/+96
| | | | | | | | | | | It's almost exactly the same code in both files, so let's have one file only. That means we need an #ifdef for the special case of 64-bit types on i386. Also take the opportunity to add a comment explaining how this works. Change-Id: I50d274fa026806ae511b1045aa8a5c25daaa0edc Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
* Rename qatomic_x86_64.h to qatomic_x86.hThiago Macieira2012-03-282-1/+1
| | | | | | | | | This is the first step in merging the i386 and x86-64 architectures. The next commit will bring i386 support into qatomic_x86.h. Change-Id: I24105ea70f3fc29b3fb779a70053f99117440573 Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
* Merge master into api_changesKent Hansen2012-03-271-0/+2
|\ | | | | | | | | | | | | | | | | | | Conflicts: src/corelib/global/qisenum.h src/dbus/qdbusconnection_p.h src/widgets/kernel/qwidget.cpp tests/auto/other/qaccessibility/tst_qaccessibility.cpp Change-Id: I85102515d5fec835832cc20ffdc5c1ba578bd01d
| * Add the missing 'itt eq' instructions to the ARM atomics.Thiago Macieira2012-03-241-0/+2
| | | | | | | | | | | | | | This affected the 16- and 64-bit sizes only. Must have been a C&P failure. Change-Id: If7b1e534a61d812226a6e4970909b53b0cc5a9a6 Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
* | Use ADD/SUB instructions on x86 and x86-64 atomics instead of INC/DECThiago Macieira2012-03-262-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the Intel Optimization Manual section 3.5.1.1 Use of INC and DEC Instructions, those instructions modify only part of the flags register, so they mey introduce unnecessary data dependencies on previous flag-setting operations so that the resulting flags are computed. Preferring ADD and SUB (rule 33) is recommended. However, we don't do it for 16-bit integers. The reason is that the presence of the 0x66 prefix may trigger a slower decoding codepath in the processor (up to 6 cycles, as opposed to 1). The same Intel manual talks about Length-Changing Prefix, which applies in particular to instructions with 16-bit immediates. The assembler generally produces uses the 8-bit immediate variant of the ADD and SUB instructions, but to be on the safe side, we prefer to use INC and DEC here. Change-Id: Ic03236ac600a5b4e087614d21df5d3c666ae064e Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
* | Fix the 64-bit i386 atomic according to assembly outputThiago Macieira2012-03-261-6/+6
|/ | | | | | | | | | | | | | | | | | | | | | | | | The assembly output showed that GCC was generating some wrong code in some conditions, so update the constraints so it will do the right thing: the expectedValue constraint needs to be in/out with early clobber. In/out because cmpxchg8b really does produce output and, even if we don't care about it, GCC needs to be told that the registers used (EAX:EDX) were modified. The early clobber is necessary so it won't schedule EAX or EDX to be the same as the EBX_reg (the register we'll xchg EBX with). Since EAX and EDX are in/out and EBX can't be used, the only remaining low register for the "sete" instruction is CL. So use it directly and set ECX to be in/out too. For whatever reason, it can't find enough registers in debug mode and this expansion doesn't work. It looks like a bug though, since this requires 4 registers and one memory operand and in debug mode it must have EAX, ECX, EDX, ESI and EDI free for use. One of ESI or EDI is used to xchg EBX with, which means there must be at least one more free general register. Change-Id: I1f11e68d776bf9ad216b34ca316a53129122fabe Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
* Make loadAcquire const.Stephen Kelly2012-02-292-3/+3
| | | | | Change-Id: Iad2d60d1abe363a3b85eaf152861d0979a997d81 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Rename Q_PROCESSOR_POWERPC to Q_PROCESSOR_POWERBradley T. Hughes2012-02-203-11/+9
| | | | | | | | | IBM's POWER and the PowerPC architecture have been merged into a single ISA, the Power ISA (see http://www.power.org). Use this unified name in Qt. Change-Id: Ia41492b0031d890843e43c5f7ecd1e60c65bb75b Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove usages of QT_ARCH and QT_ARCH_* from qtbaseBradley T. Hughes2012-02-172-9/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The architecture is detected at compile time based on the predefined macros from the compiler. Don't use QT_ARCH in .pro, .pri, or .prf files. The PNG_NO_ASSEMBLER_CODE define from libpng.pri is not present in the current copy of src/3rdparty/libpng, so no change in functionality is expected. The conditional for the SUPPORT_JIT define in pcre.pri is moved to src/3rdparty/pcre/config.h, again so that we can use the compiler's predefined macros to detect the architecture at compile time. Replace QT_ARCH_ARM, QT_ARCH_MIPS, and QT_ARCH_SPARC with their Q_PROCESSOR_* equivalents. Replace QT_ARCH_INTEGRITY, QT_ARCH_VXWORKS, and QT_ARCH_WINDOWSCE with their Q_OS_* equivalents. Note that this commit also effectively disables the SPARC atomic implementation. An inline implementation for SPARC needs to be added, or we remove the current code and instead rely on the GCC intrinsic or C++11 std::atomic support on SPARC. Note also that this commit does not remove QT_ARCH from configure or qconfig.h. This will continue to be set until all Qt 5 projects can be moved away from using QT_ARCH. Change-Id: I5de747cc4436d21941329974cff3016970f497b8 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com> Reviewed-by: Lars Knoll <lars.knoll@nokia.com>
* Cleanup HEADERS+=... in src/corelib/arch/arch.priBradley T. Hughes2012-02-131-23/+18
| | | | | | | | | Include all qatomic_*.h files in HEADERS, since we don't know which include the compiler will end up choosing in the end (operating system specific includes are still conditionally included, though). Change-Id: I4241e40ad51d34dede04be0c4ee95378d6f3d037 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Add src/corelib/arch/qatomic_unix.h and qatomic_unix.cppBradley T. Hughes2012-02-133-0/+205
| | | | | | | | | | | | This provides a fallback implementation on UNIX when the Q_PROCESSOR_* and Q_CC_*/Q_COMPILER_* checks fail to find an implementation. Note that we always compile qatomic_unix.cpp, but code is only included when QATOMIC_UNIX_H is defined (meaning the checks above did not find an implementation). Change-Id: I8ce047847206003b4fa96eb3fb76b1c2ffbc2dfc Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove qatomic_arch.hBradley T. Hughes2012-02-1310-72/+15
| | | | | | | | | | | | Make qbasicatomic.h include the OS/compiler/processor dependent implementation. For implementations that have not yet been ported to declare a QAtomicOps, they need to #include <QtCore/qoldbasicatomic.h>, and the new QBasicAtomicInteger and QBasicAtomicPointer should not be declared. Change-Id: Ia951834484c9f8dfa75131592e5e716b68ff989b Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove the generic atomic implementationBradley T. Hughes2012-02-136-546/+2
| | | | | | | | | This implementation is not used on Windows, and needs to be updated on UNIX for processors that we do not support (this will be done in a separate commit). Change-Id: I471d0ed00f4e8b89ecfa400796a2dbe2330935c6 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove HP PA-RISC atomic implementation.Bradley T. Hughes2012-02-136-463/+0
| | | | | | | | | | | This architecture is obsolete and discontinued. Support for PA-RISC can be re-added if needed, but it would be preferred to use the GCC intrinsic support from qatomic_gcc.h (on Linux/HPPA, for example). Change-Id: I952e521a2c8c68840df0d44843b5487d5c20b135 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove the SH atomic implementation...Bradley T. Hughes2012-02-135-409/+0
| | | | | | | | | | | | ... but keep SH-4a, which provides a more efficient implementation. The implementation removed here was very similar to the code removed by commit dc5388e79b71d796c1207681235cf007c39810bd. Support for SH can be provided by qatomic_gcc.h, or re-added in the future if absolutely necessary. Change-Id: Ic38b57c9513fc9c3c99ba7e102780a3939b735b9 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove out-of-line atomic implementation for PowerPCBradley T. Hughes2012-02-136-1622/+1
| | | | | | | | | | | | | | | | Only support inline assembler with GCC. Support for xlC or other compilers is not provided or tested. The files in src/corelib/arch/vxworks only supported out-of-line PowerPC, so remove it as well. The xlC compiler seems to support GNU-style inline assembly, which we prefer. Anyone wishing to support that compiler again should first test if the inline assembly (the prefered method) works. See http://publib.boulder.ibm.com/infocenter/lnxpcomp/v8v101/topic/com.ibm.xlcpp8l.doc/language/ref/asm.htm#asm Change-Id: I70e56c0b06428bfb6538ca5e101baebd870f92f5 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove out-of-line atomic implementation for AlphaBradley T. Hughes2012-02-133-367/+2
| | | | | | | | | This implementation has not been tested or supported at all during the Qt 4.x lifetime. Do not bring it with us into Qt 5.x. Only inline assembler with GCC is supported. Change-Id: I31b48721bb7f4c96f4a777da604d80cc63c6fd79 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Use Q_PROCESSOR_* when chosing an atomic implementationBradley T. Hughes2012-02-083-77/+1
| | | | | | | | | | Use the new Q_PROCESSOR_* macros to decide which headers to include in the atomic implementation. This also removes qatomic_arm.h, which isn't needed anymore, just select the correct qatomic_armv*.h from qbasicatomic.h Change-Id: I954848feafb8c420949d066ffcee1dd2b271e13b Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Silence syncqt warnings for atomic implementation headersBradley T. Hughes2012-02-0612-0/+58
| | | | | | | | | | Most of these headers are either forwarding headers, or we explicitly stop syncqt so that it doesn't generate class includes for the atomic implementation. Either way, syncqt doesn't see the QT_END_* (and sometimes not QT_BEGIN_*), which this commit fixes. Change-Id: Icc8da6f384f38b1ff4eb265c731ce2f2ed92a1a3 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove empty src/corelib/arch subdirectoriesBradley T. Hughes2012-02-034-12/+0
| | | | | | | | | | The bfin, integrity, s390, and sh4a directories included an empty arch.pri, which is not necessary. Remove these directories and arch.pri files. Change-Id: I016dcef63e4b9fb4c14cc1fa7b9b91cba2080dbb Reviewed-by: Giuseppe D'Angelo <dangelog@gmail.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove src/corelib/arch/nacl/* and qatomic_nacl.hBradley T. Hughes2012-02-034-258/+0
| | | | | | | | | | This implementation uses the GCC __sync_* intrinsics, which we do not need to duplicate after commit 2bbd2262b3974fb4e39341a23e40ffdf1655ebe9 (which added qatomic_gcc.h). Change-Id: I59b6e4a03e83f58f4145a5ab2bfd635fe9ab686f Reviewed-by: Morten Johan Sørvig <morten.sorvig@nokia.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove src/corelib/arch/ia64/*Bradley T. Hughes2012-02-032-78/+0
| | | | | | | | | The out-of-line q_atomic_test_and_set_(int|ptr) functions are no longer declared after commit 1955353149781a064bc053b86be6e221b159d4ee. They appear to have never been used either. Remove them. Change-Id: Ia8dfa1f585f2370091b4fd93aaf98cb10241bf31 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove src/corelib/arch/i386/* and src/corelib/arch/x86_64/*Bradley T. Hughes2012-02-036-303/+2
| | | | | | | | We do not want to support out-of-line QAtomic* implementations. Remove these from the i386 and x86_64 implementations. Change-Id: Ib6a9614b7b11bf6bccc9054b177357afd83e33e6 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove src/corelib/arch/avr32/* and qatomic_avr32.hBradley T. Hughes2012-02-034-258/+0
| | | | | | | | | This implementation uses the GCC __sync_* intrinsics, which we do not need to duplicate after commit 2bbd2262b3974fb4e39341a23e40ffdf1655ebe9 (which added qatomic_gcc.h). Change-Id: I2cab86deacad1c37f17f0c5836d9faf2ad366495 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove src/corelib/arch/mips/*Bradley T. Hughes2012-02-033-296/+0
| | | | | | | | | Commit 99fb1bea49c4de5cf3143af59f8c96a92980e58f removed the use of the old, out-of-line q_atomic_* implementation. Remove these functions from the library. Change-Id: I0b239bf779e0545cb5558862e3a40f6e95fdcbd9 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove src/corelib/arch/arm/*Bradley T. Hughes2012-02-032-76/+0
| | | | | | | | | After commit dc5388e79b71d796c1207681235cf007c39810bd, which removed support for non-EABI, qt_atomic_yield() and q_atomic_lock are no longer used. Remove them. Change-Id: I0f405ae63d7903c222fc2b829887207885be0a03 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove #include "qatomic_macosx.h"Bradley T. Hughes2012-02-031-2/+0
| | | | | | | This file was removed in commit 68e5fd9ebc8a3f510e3144e981a0cb358945fb9c Change-Id: I76671f79432204c28ffa7488871d0eef07cc8dca Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Rename qatomic_windows.h to qatomic_msvc.hBradley T. Hughes2012-02-035-74/+7
| | | | | | | | | | The QT_ARCH_WINDOWS(CE) define(s) aren't used to control which header to include anymore, so just remove it. We also do not need the empty src/corelib/arch/windows/arch.pri. Change-Id: I5400fc852af31907e533d0278540b8cd3da391cb Reviewed-by: Friedemann Kleint <Friedemann.Kleint@nokia.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Port the Windows atomic implementation to use QGenericAtomicOpsBradley T. Hughes2012-02-021-214/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | First, we do not need to have the QT_INTERLOCKED_REMOVE_VOLATILE(a) macro anymore either, since the value stored in QBasicAtomicInteger is not volatile. Windows provides Interlocked*Pointer() functions in some configurations, so we provide a partial specialization of QAtomicOps for pointer types. For integer types, QAtomicOps selects an implementation based on the size of the type. At the moment, we only support 32-bit types, but it will be possible to add 64-bit later. Note that the 32-bit specialization of QAtomicOpsBySize declares the Type typedef as long, not int, since the Windows Interlocked*() API takes parameters as longs and long pointers. Since this typedef differs from the type given to QBasicAtomicInteger<T> by the QBasicAtomicInt typedef, we need to templatise the _q_value parameter separately from the other arguments in QGenericAtomicOps. This templatisation would be necessary to port other architectures, such as PA_RISC, where we need to have an int[4] array in the atomic type while the arguments do not need this array. Change-Id: Id71fa1ae334da2023553cb402b45e6c285f1d344 Reviewed-by: Friedemann Kleint <Friedemann.Kleint@nokia.com> Reviewed-by: João Abecasis <joao.abecasis@nokia.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Avoid non-standard indentation of license headers.Jason McDonald2012-01-301-39/+39
| | | | | | | | The strange indentation has made maintenance of license headers difficult on several occasions. Change-Id: Ib29a7e5275e2c7a2c13a3f32fd2479f34d3353ca Reviewed-by: Rohan McGovern <rohan.mcgovern@nokia.com>
* Remove "All rights reserved" line from license headers.Jason McDonald2012-01-3042-34/+42
| | | | | | | | | | As in the past, to avoid rewriting various autotests that contain line-number information, an extra blank line has been inserted at the end of the license text to ensure that this commit does not change the total number of lines in the license header. Change-Id: I311e001373776812699d6efc045b5f742890c689 Reviewed-by: Rohan McGovern <rohan.mcgovern@nokia.com>
* Add a set of atomics based on C++11's std::atomicThiago Macieira2012-01-282-1/+248
| | | | | | | | | | | | | | | | | | | | | The C++11 std::atomic type is very close to our API, to the point one has to wonder if the committe was inspired by it. It provides all of the memory semantics that Qt requires and more, plus some compare-and-swap operations that we don't use. The idea of returning the actual value in the event of a failed compare-and-swap is actually quite good, as often we'll retry with it. We just couldn't come up with a good name (fetchAndTestAndSet?). The C++11 atomics require that the compiler support constexpr as well, since std::atomic itself isn't required by the standard to be trivially-constructible (in fact, it has a constexpr constructor in the standard). For that reason, we need constexpr so we can add a constructor to QBasicAtomic too. Change-Id: I12c51455ba73350a6f7501aacc2ca7681c4369dd Reviewed-by: Thiago Macieira <thiago.macieira@intel.com> Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
* Add a set of atomics based on GCC intrinsicsThiago Macieira2012-01-282-1/+131
| | | | | | | | | | | | | | | | | | | | | | | | | With this implementation, we can have Qt run on any architecture that GCC supports without having to write specialised code. However, on some architectures, the code that GCC generates is not optimal: it uses locking on ARMv5 and it's always fully-ordered. For that reason, it appears after the Qt native assembly implementations (it's a fallback, not an override). Since they all have fully-ordered memory semantics, we define only the xxxRelaxed functions. The exception is __sync_lock_and_test, which has acquire semantics, so we need to define the Release and Ordered versions too. On some architectures, GCC can support atomics on types different than 32-bit and pointer-sized (like x86, x86-64, ARM and even MIPS). However, there's no standardised way of telling: GCC seems to define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2,4,8} if those operations are present, but I couldn't find it on the ARM compiler (it was there for i386, x86-64, IA-64 and MIPS). Change-Id: I55ff7a7c0cfc6388b7ad8e2c0dedecffdf2a3e01 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com> Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
* Remove the 'macosx' archBradley T. Hughes2012-01-264-233/+2
| | | | | | | | | | | | | The new atomic implementation chooses which header to include based on what #define's are set by the compiler (i.e. __x86_64__ or __i386__). Because of this, the qatomic_macosx.h header isn't used anymore. This also means that the configure script does not need to use or look for this file anymore, it should just use the normal uname -m detection. Change-Id: Ibf275488735483268286196952299c0e496dfd1f Reviewed-by: Morten Johan Sørvig <morten.sorvig@nokia.com> Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
* Remove use of QT_MODULE from libraryGunnar Sletta2012-01-252-16/+0
| | | | | | | | | | These defines were there to aid in the commercial licensing scheme we used long ago, and are no longer needed. Keep a QT_MODULE(x) define so other modules continue compiling. Change-Id: I8fd76cd5270df8f14aee746b6cf32ebf7c23fec7 Reviewed-by: Lars Knoll <lars.knoll@nokia.com>
* Remove Symbian code from QtCore.Xizhi Zhu2012-01-243-317/+1
| | | | | Change-Id: I9abdc674bcfa7bb38ce27c5213c5a672f59e63d5 Reviewed-by: Lars Knoll <lars.knoll@nokia.com>
* Port the IA-64 atomics to the new QBasicAtomicXXX architectureThiago Macieira2012-01-242-350/+618
| | | | | | | | | | | | | | | | The IA-64 architecture supports the actual memory ordering semantics in many instructions, but not all. We actually implement the functions for all operations, so we get the best possible output. It does support proper load-acquire and store-release semantics, but we don't need instructions for it: the ABI requires that a volatile load be acquire and a volatile store be release. The Intel and HP compiler codepaths are rewritten, but untested. Change-Id: I7aa62a4ec65f63a97d1bbd8418bb2492c2be465f Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Port the MIPS atomics to the new QBasicAtomicXXX architectureThiago Macieira2012-01-242-692/+144
| | | | | | | | | | | | | | | The LL/SC instructions are only present on MIPS II and up, so don't pretend to support MIPS I. The previous implementation emitted the instructions by telling the assembler to change instruction sets. Now, the user must pass an -march= option to GCC telling it which architecture or processor is being targetted. On MIPS64, the 64-bit implementation allows supporting for long long too. Change-Id: I6dae6f8f61e563aba6a663227d91c5ddf554aa6a Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Port the ARM atomics to the new QBasicAtomicXXX architectureThiago Macieira2012-01-243-518/+425
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation is divided in two files, as it used to be in the previous implementation: one for ARMv5, one for ARMv6 and up. For the ARMv5 implementation: Drop the non-Linux EABI version of the atomics, as it's not ABI-compatible with the ARMv6 and ARMv7 implementations. This means this ARMv5 implementation only works on Linux. If other systems implement kernel helpers like Linux, they can be added too. We use the __kernel_cmpxchg located at 0xffff0fc0 to implement the operations, except for fetchAndStore, for which we use the SWP instruction. Also introduce the use of __kernel_dmb (at 0xffff0fa0) for the memory barrier. Now this code is SMP-safe even when built with ARMv5. The kernel cmpxchg helper was introduced in Linux 2.6.12, whereas the dmb helper was introduced in 2.6.15. That means 2.6.15 is the minimum version now. For ARMv6 and up: Introduce byte, half-word and doubleword atomics that work on ARMv6K and up. For ARMv6 specifically, the memory barrier instruction (DMB) isn't present, so we need to accomplish the same with the MCR coprocessor instruction. Change-Id: Ife7f9b920bcc7d1eef7611761f6c59ea940ec7df Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-03 23:13:43 +0000