| Commit message (Collapse) | Author | Age | Files | Lines |
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This has apparently never worked for any negative value. That's because
the compiler sign-extends the incoming expectedValue to fill the 32-bit
register, instead of zero-extending it, and it also expects any returned
values to also be sign-extended.
Task-number: QTBUG-37031
Change-Id: I836eddba7b1acc56bb0ac1d41de7001d06255b9b
Reviewed-by: Sergio Ahumada <sahumada@blackberry.com>
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Two changes broke compilation on armv5, where we're currently
not CI-testing:
634f82f1f1fda7983abf70b58e43c580b1f01df0 changed the signature
in a function definition without changing its declaration, while
it was actually intending to add this as a new overload.
bfe0db6fbea6376dbe395af6d76995a54bbc3b49 added an #error
condition without fixing compilation on armv5. I don't know
if the fix is correct, but at least it compiles.
Task-number: QTBUG-37034
Change-Id: If99142fafb9bd55afc20b17f8b3cce5ee0ffec13
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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This is extremely useful, since the most common action after a failed
compare-and-swap is to loop around, trying again with the current
value as found in memory.
Code currently written as:
do {
Type value = atomic.load();
...
} while (!atomic.testAndSetRelaxed(value, desired));
Becomes:
Type value = atomic.load();
do {
...
} while (!atomic.testAndSetRelaxed(value, desired, value));
In most CPU architectures, the value that was found in memory is known
to the compare-and-swap code, so this is more efficient than the
previous code. In architectures where the value is not known, the new
code is no worse than before.
The implementation sometimes modified an existing function, sometimes
it added a new one, depending on whether more registers were needed in
the assembly (like ARMv6-7), the code became more complex (ARMv5), the
optimizer failed (C++11), or it was just plain equivalent (MIPS).
Change-Id: I7d6d200ea9746ec8978a0c1e1969dbc3580b9285
Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com>
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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This simplifies the code a lot and avoids silly mistakes where a
specific integer type is missing (such as char16_t).
Change-Id: Id91dfd1919e783e0a9af7bfa093ca560a01b22d1
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
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No need to redefine everywhere, since they're required to be supported.
Change-Id: I2bdbbd0b0c44871e3bd0edcf0289fc58dd50ff31
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
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This is already implemented in qatomic_x86.h, qatomic_ia64.h,
qatomic_mips.h, qatomic_armv6.h, and qatomic_cxx11.h. For
qatomic_msvc.h, we've just fixed it.
For qatomic_gcc.h, we know that the compiler supports it, so just add
it. According to the GCC manual, it might print a warning on some
platforms, so we only enable that on 64-bit builds.
For qatomic_unix.h, the support was missing (along with support for
unsigned 32-bit), so this commits adds it.
For qatomic_armv5.h, the platform does not always support 64-bit
atomics, but ARMv5 cannot compile in 64-bit mode anyway.
Change-Id: Ia8b3b5c641f11e5df05937fe7442be0a223174ef
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
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MSVC provides the necessary functions / intrinsics for 16- and 64-bit
operations. It has some support for 8-bit too, but the most important
functions seem to be missing...
Change-Id: I177b4eb2a2cf14d716b78c94f9d6a9b11aea1b84
Reviewed-by: Friedemann Kleint <Friedemann.Kleint@digia.com>
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
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the diff -w for this commit is empty.
Started-by: Thiago Macieira <thiago.macieira@intel.com>
Change-Id: I77bb84e71c63ce75e0709e5b94bee18e3ce6ab9e
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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The new atomic code was introduced in Qt 5.0. The platforms that did not
get ported were announced as deprecated in Qt 5.2. The code is now
removed in Qt 5.3.
The status for the platform/compiler/OS combinations affected is:
* Linux with GCC or Clang: still compiles on all platforms
(via qatomic_cxx11.h or qatomic_gcc.h)
* INTEGRITY with Green Hills compiler: no longer compiles
* Solaris on UltraSPARC, with Sun Studio: no longer compiles
* AIX on POWER5 or 6, with IBM Visual Age: no longer compiles
(probably did not compile Qt 5.0 either)
* VxWorks in kernel mode: no longer compiles
[ChangeLog][General] Support for the following platforms has been
removed, due to lack of interest in updating support: INTEGRITY,
VxWorks, Solaris on UltraSPARC (with the Sun Studio compiler suite), AIX
on POWER processors (with IBM Visual Age compiler suite).
Change-Id: I8a961385fd95011c016b2b1eec52034794dae3e1
Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
Reviewed-by: Konstantin Ritt <ritt.ks@gmail.com>
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
Reviewed-by: Marc Mutz <marc.mutz@kdab.com>
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They're now required as per the documentation. They should have been
present when this was created...
Change-Id: If52bc91e942306ef0fa7b1b41b739d897c9a1ea1
Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
Reviewed-by: Marc Mutz <marc.mutz@kdab.com>
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At least with GCC, the use of cmpxchg8b in inline assembly is
unreliable. The instruction requires 5 registers to be used and
sometimes GCC complains that it runs out of them.
qatomic_x86.h:424:33: error: can’t find a register in class ‘GENERAL_REGS’ while reloading ‘asm’
qatomic_x86.h:424:33: error: ‘asm’ operand has impossible constraints
Change-Id: Ie5414f3bccc6e559c7eec93beabe8663ab40271f
Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
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In qatomic_cxx11, the 'Type' is std::atomic<T>, whose fetch_add method,
used in fetchAndAdd*(), already does the right thing for T* with sizeof(T) > 1.
The code, however, applied 'AddScale' to the 'valueToAdd', thus becoming
incompatible with normal pointer arithmetics.
This is very apparent when one goes to the length of actually testing
qatomic_cxx11 with tst_QAtomicPointer (which is non-trivial, since the
-c++11 configure option currently doesn't have an effect on tests/auto).
To fix, remove the AddScale factor.
Change-Id: I7507203af3b7df31d8322b31a6a1a33ca847d224
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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Both Clang and ICC complain about the use of those atomics when used
with a forward-declared pointee. GCC doesn't, which makes me think
it's a GCC bug.
When using QBasicAtomicPointer<Foo> with these atomics, the _q_value
member causes the instantiation of QAtomicOps<Foo>, which causes the
instantiation of the regular member function
QAtomicOps<Foo>::fetchAndAddRelaxed. The problem is that function
takes a QAtomicAdditiveType<Foo>::AdditiveT as parameter, which
requires sizeof(Foo). Clang 3.3 and ICC 14 correctly expand and
complain. GCC 4.7-4.9 apparently don't.
The fix is to apply the same trick we used for the other atomics:
change all ops functions (including fetchAndAddRelaxed) to be member
templates. That way, they can't be expanded until the actual use.
Clang errors:
qgenericatomic.h:73:33: error: invalid application of 'sizeof' to an incomplete type 'QMutexData'
qatomic_gcc.h:136:48: note: in instantiation of template class 'QAtomicAdditiveType<QMutexData *>' requested here
qbasicatomic.h:272:22: note: in instantiation of template class 'QAtomicOps<QMutexData *>' requested here
ICC errors:
qgenericatomic.h(73): error: incomplete type is not allowed
detected during:
instantiation of class "QAtomicAdditiveType<T *> [with T=QMutexData]" at line 111 of "qatomic_cxx11.h"
instantiation of class "QAtomicOps<T> [with T=QMutexData *]" at line 272 of "qbasicatomic.h"
Found-by: Tor Arne
Change-Id: I9b10648cd47109a943b34a4c9926d77cd0c4fe12
Reviewed-by: Tor Arne Vestbø <tor.arne.vestbo@digia.com>
Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
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It is deprecated and clang is starting to warn about it.
Patch mostly generated by clang itself, with some careful grep
and sed for the platform-specific parts.
Change-Id: I8058e6db0f1b41b33a9e8f17a712739159982450
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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Remove all trailing whitespace from the following list of files:
*.cpp *.h *.conf *.qdoc *.pro *.pri *.mm *.rc *.pl *.qps *.xpm *.txt *README
excluding 3rdparty, test-data and auto generated code.
Note A): the only non 3rdparty c++-files that still
have trailing whitespace after this change are:
* src/corelib/codecs/cp949codetbl_p.h
* src/corelib/codecs/qjpunicode.cpp
* src/corelib/codecs/qbig5codec.cpp
* src/corelib/xml/qxmlstream_p.h
* src/tools/qdoc/qmlparser/qqmljsgrammar.cpp
* src/tools/uic/ui4.cpp
* tests/auto/other/qtokenautomaton/tokenizers/*
* tests/benchmarks/corelib/tools/qstring/data.cpp
* util/lexgen/tokenizer.cpp
Note B): in about 30 files some overlapping 'leading tab' and
'TAB character in non-leading whitespace' issues have been fixed
to make the sanity bot happy. Plus some general ws-fixes here
and there as asked for during review.
Change-Id: Ia713113c34d82442d6ce4d93d8b1cf545075d11d
Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com>
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QtCore has a few headers that, though public, aren't meant to be
included directly. Those are the atomic headers, the three _impl.h
headers and qt_windows.h.
QtGui includes two OpenGL headers that don't compile on their own.
Other libraries should not have headers like that (but they do,
something we need to fix eventually).
Change-Id: I55e4eb057748f47df927ee618f9409acbc189cc1
Reviewed-by: Sean Harmer <sean.harmer@kdab.com>
Reviewed-by: Gunnar Sletta <gunnar.sletta@digia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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Change-Id: Ie9f98e5f5a08908d9d99e04bdc95fd506cc4a51e
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
Reviewed-by: Paul Olav Tvete <paul.tvete@digia.com>
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The macro was made empty in ba3dc5f3b56d1fab6fe37fe7ae08096d7dc68bcb
and is no longer necessary or used.
Discussed-on: http://lists.qt-project.org/pipermail/development/2013-January/009284.html
Change-Id: Id2bb2e2cabde059305d4af5f12593344ba30f001
Reviewed-by: Laszlo Papp <lpapp@kde.org>
Reviewed-by: Jędrzej Nowacki <jedrzej.nowacki@digia.com>
Reviewed-by: hjk <hjk121@nokiamail.com>
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refs/staging/dev
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Change-Id: Ic804938fc352291d011800d21e549c10acac66fb
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
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VxWorks does not support to globally lock and unlock the scheduler from
process. In kernel mode (DKM) above functions disable preemption from
requested task and such functionality does not exist for process.
Change-Id: Id41eab4c1973e4181e82539d08707659e0780f99
Reviewed-by: Samuel Rødal <samuel.rodal@digia.com>
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Change copyrights and license headers from Nokia to Digia
Change-Id: If1cc974286d29fd01ec6c19dd4719a67f4c3f00e
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
Reviewed-by: Sergio Ahumada <sergio.ahumada@digia.com>
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Those are regular, integer types, of 16- and 32-bit width,
respectively. C++11's std::atomic supports them, so we should too.
C++11 also supports wchar_t, but since that type's size can change, I
don't feel like support for it in Qt is pressing.
Change-Id: I945b641c91a8a98be82715f878c382dee58ac98b
Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
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This allows one to write code that depends on these values at
compile-time.
Change-Id: I7d78524ed9c70d4141360496d1d764dcbfa92e62
Reviewed-by: Marc Mutz <marc.mutz@kdab.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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Actually, only the "new" atomics are marked. The old implementation,
based on qoldbasicatomic.h is unchanged, but should still work without a
problem.
The following configurations were tested and do work:
- x86 64-bit
- x86 32-bit
- generic GCC
- generic C++11 std::atomic
- bootstrap
- ARMv6 and 7
- MIPS
- MSVC 2010 32-bit
- MSVC 2010 64-bit
The only two configurations untested are IA-64 and ARMv5. Except for
MSVC, all configurations were tested with GCC 4.6 (MIPS and ARM) and 4.7
(x86 and generics).
Change-Id: Iecbfeacd9d20b535453e91335165e9a221e0b47e
Reviewed-by: Marc Mutz <marc.mutz@kdab.com>
Reviewed-by: Lars Knoll <lars.knoll@nokia.com>
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This is so we can insert valgrind (helgrind) annotation macros. They
require the actual address of the variable to work.
Change-Id: I988f6a46385ad58143c53ad34b6cf0f58be2cdb8
Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
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Change-Id: I19d3b2e9a5180b13deb828b55195404ef20be295
Reviewed-by: Daniel Teske <daniel.teske@nokia.com>
Reviewed-by: Giuseppe D'Angelo <giuseppe.dangelo@kdab.com>
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qatomic_msvc.h declares some Windows intrinsic functions which should
not be in the Qt namespace.
Change-Id: I1b2f91798159c08cf167ee3d1ed2818c12c9b833
Reviewed-by: Friedemann Kleint <Friedemann.Kleint@nokia.com>
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Inspired by
https://bugreports.qt-project.org/secure/attachment/26020/qt_atomic_sparc64.patch
Task-number: QTBUG-22479
Change-Id: Ie3275df96c639d6a75e05f70fe5745aeb34457f9
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
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It's almost exactly the same code in both files, so let's have one file
only. That means we need an #ifdef for the special case of 64-bit types
on i386.
Also take the opportunity to add a comment explaining how this works.
Change-Id: I50d274fa026806ae511b1045aa8a5c25daaa0edc
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
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This is the first step in merging the i386 and x86-64
architectures. The next commit will bring i386 support into
qatomic_x86.h.
Change-Id: I24105ea70f3fc29b3fb779a70053f99117440573
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
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Conflicts:
src/corelib/global/qisenum.h
src/dbus/qdbusconnection_p.h
src/widgets/kernel/qwidget.cpp
tests/auto/other/qaccessibility/tst_qaccessibility.cpp
Change-Id: I85102515d5fec835832cc20ffdc5c1ba578bd01d
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This affected the 16- and 64-bit sizes only. Must have been a C&P failure.
Change-Id: If7b1e534a61d812226a6e4970909b53b0cc5a9a6
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
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According to the Intel Optimization Manual section 3.5.1.1 Use of INC
and DEC Instructions, those instructions modify only part of the flags
register, so they mey introduce unnecessary data dependencies on
previous flag-setting operations so that the resulting flags are
computed. Preferring ADD and SUB (rule 33) is recommended.
However, we don't do it for 16-bit integers. The reason is that the
presence of the 0x66 prefix may trigger a slower decoding codepath in
the processor (up to 6 cycles, as opposed to 1). The same Intel manual
talks about Length-Changing Prefix, which applies in particular to
instructions with 16-bit immediates. The assembler generally produces
uses the 8-bit immediate variant of the ADD and SUB instructions, but
to be on the safe side, we prefer to use INC and DEC here.
Change-Id: Ic03236ac600a5b4e087614d21df5d3c666ae064e
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
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The assembly output showed that GCC was generating some wrong code in
some conditions, so update the constraints so it will do the right
thing: the expectedValue constraint needs to be in/out with early
clobber. In/out because cmpxchg8b really does produce output and, even
if we don't care about it, GCC needs to be told that the registers
used (EAX:EDX) were modified. The early clobber is necessary so it
won't schedule EAX or EDX to be the same as the EBX_reg (the register
we'll xchg EBX with).
Since EAX and EDX are in/out and EBX can't be used, the only remaining
low register for the "sete" instruction is CL. So use it directly and
set ECX to be in/out too.
For whatever reason, it can't find enough registers in debug mode and
this expansion doesn't work. It looks like a bug though, since this
requires 4 registers and one memory operand and in debug mode it must
have EAX, ECX, EDX, ESI and EDI free for use. One of ESI or EDI is
used to xchg EBX with, which means there must be at least one more
free general register.
Change-Id: I1f11e68d776bf9ad216b34ca316a53129122fabe
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
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Change-Id: Iad2d60d1abe363a3b85eaf152861d0979a997d81
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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IBM's POWER and the PowerPC architecture have been merged into a single
ISA, the Power ISA (see http://www.power.org). Use this unified name in
Qt.
Change-Id: Ia41492b0031d890843e43c5f7ecd1e60c65bb75b
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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The architecture is detected at compile time based on the predefined
macros from the compiler. Don't use QT_ARCH in .pro, .pri, or .prf
files. The PNG_NO_ASSEMBLER_CODE define from libpng.pri is not present
in the current copy of src/3rdparty/libpng, so no change in
functionality is expected.
The conditional for the SUPPORT_JIT define in pcre.pri is moved to
src/3rdparty/pcre/config.h, again so that we can use the compiler's
predefined macros to detect the architecture at compile time.
Replace QT_ARCH_ARM, QT_ARCH_MIPS, and QT_ARCH_SPARC with their
Q_PROCESSOR_* equivalents.
Replace QT_ARCH_INTEGRITY, QT_ARCH_VXWORKS, and QT_ARCH_WINDOWSCE with
their Q_OS_* equivalents.
Note that this commit also effectively disables the SPARC atomic
implementation. An inline implementation for SPARC needs to be added,
or we remove the current code and instead rely on the GCC intrinsic or
C++11 std::atomic support on SPARC.
Note also that this commit does not remove QT_ARCH from configure or
qconfig.h. This will continue to be set until all Qt 5 projects can be
moved away from using QT_ARCH.
Change-Id: I5de747cc4436d21941329974cff3016970f497b8
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
Reviewed-by: Lars Knoll <lars.knoll@nokia.com>
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Include all qatomic_*.h files in HEADERS, since we don't know which
include the compiler will end up choosing in the end (operating system
specific includes are still conditionally included, though).
Change-Id: I4241e40ad51d34dede04be0c4ee95378d6f3d037
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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This provides a fallback implementation on UNIX when the Q_PROCESSOR_*
and Q_CC_*/Q_COMPILER_* checks fail to find an implementation.
Note that we always compile qatomic_unix.cpp, but code is only included
when QATOMIC_UNIX_H is defined (meaning the checks above did not find an
implementation).
Change-Id: I8ce047847206003b4fa96eb3fb76b1c2ffbc2dfc
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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Make qbasicatomic.h include the OS/compiler/processor dependent
implementation.
For implementations that have not yet been ported to declare a
QAtomicOps, they need to #include <QtCore/qoldbasicatomic.h>, and the
new QBasicAtomicInteger and QBasicAtomicPointer should not be declared.
Change-Id: Ia951834484c9f8dfa75131592e5e716b68ff989b
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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This implementation is not used on Windows, and needs to be updated
on UNIX for processors that we do not support (this will be done in
a separate commit).
Change-Id: I471d0ed00f4e8b89ecfa400796a2dbe2330935c6
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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This architecture is obsolete and discontinued.
Support for PA-RISC can be re-added if needed, but it would be preferred
to use the GCC intrinsic support from qatomic_gcc.h (on Linux/HPPA, for
example).
Change-Id: I952e521a2c8c68840df0d44843b5487d5c20b135
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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... but keep SH-4a, which provides a more efficient implementation. The
implementation removed here was very similar to the code removed by
commit dc5388e79b71d796c1207681235cf007c39810bd.
Support for SH can be provided by qatomic_gcc.h, or re-added in the
future if absolutely necessary.
Change-Id: Ic38b57c9513fc9c3c99ba7e102780a3939b735b9
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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Only support inline assembler with GCC. Support for xlC or other
compilers is not provided or tested. The files in
src/corelib/arch/vxworks only supported out-of-line PowerPC, so
remove it as well.
The xlC compiler seems to support GNU-style inline assembly, which we
prefer. Anyone wishing to support that compiler again should first test
if the inline assembly (the prefered method) works. See
http://publib.boulder.ibm.com/infocenter/lnxpcomp/v8v101/topic/com.ibm.xlcpp8l.doc/language/ref/asm.htm#asm
Change-Id: I70e56c0b06428bfb6538ca5e101baebd870f92f5
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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This implementation has not been tested or supported at all during
the Qt 4.x lifetime. Do not bring it with us into Qt 5.x. Only
inline assembler with GCC is supported.
Change-Id: I31b48721bb7f4c96f4a777da604d80cc63c6fd79
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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Use the new Q_PROCESSOR_* macros to decide which headers to include in
the atomic implementation. This also removes qatomic_arm.h, which isn't
needed anymore, just select the correct qatomic_armv*.h from
qbasicatomic.h
Change-Id: I954848feafb8c420949d066ffcee1dd2b271e13b
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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Most of these headers are either forwarding headers, or we explicitly
stop syncqt so that it doesn't generate class includes for the atomic
implementation. Either way, syncqt doesn't see the QT_END_* (and
sometimes not QT_BEGIN_*), which this commit fixes.
Change-Id: Icc8da6f384f38b1ff4eb265c731ce2f2ed92a1a3
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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The bfin, integrity, s390, and sh4a directories included an empty
arch.pri, which is not necessary. Remove these directories and arch.pri
files.
Change-Id: I016dcef63e4b9fb4c14cc1fa7b9b91cba2080dbb
Reviewed-by: Giuseppe D'Angelo <dangelog@gmail.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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This implementation uses the GCC __sync_* intrinsics, which we do not
need to duplicate after commit 2bbd2262b3974fb4e39341a23e40ffdf1655ebe9
(which added qatomic_gcc.h).
Change-Id: I59b6e4a03e83f58f4145a5ab2bfd635fe9ab686f
Reviewed-by: Morten Johan Sørvig <morten.sorvig@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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