diff options
| author | Julien Brianceau <jbriance@cisco.com> | 2014-09-05 10:44:35 +0200 |
|---|---|---|
| committer | Julien Brianceau <jbriance@cisco.com> | 2014-09-05 16:23:06 +0200 |
| commit | d41aa87d6b1164666c9f013a785bc6217ae1ced2 (patch) | |
| tree | 7d5b3c6ea2bd394b4d32a24fada6d37ed500b8d8 | |
| parent | ea22657d17a934b04c8621dc8891a1d4d80510e3 (diff) | |
[mips] Fix unaligned access in Low Level Interpreter (LLINT).
Address loads used with btbxx opcodes were wrongly converted to lw instruction
instead of lbu, leading to unaligned access on mips platforms.
Change-Id: I7b14aa40215affe582bcadade2f783769a97a7d3
Reviewed-by: Jocelyn Turcotte <jocelyn.turcotte@digia.com>
| -rw-r--r-- | Source/JavaScriptCore/offlineasm/mips.rb | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/Source/JavaScriptCore/offlineasm/mips.rb b/Source/JavaScriptCore/offlineasm/mips.rb index c0adfd029..08fd02662 100644 --- a/Source/JavaScriptCore/offlineasm/mips.rb +++ b/Source/JavaScriptCore/offlineasm/mips.rb @@ -231,9 +231,10 @@ def lowerMIPSCondBranch(list, condOp, node) [node.operands[0], MIPS_ZERO_REG, node.operands[-1]], node.annotation) elsif node.operands.size == 3 + tl = condOp[-1, 1] tmp = Tmp.new(node.codeOrigin, :gpr) list << Instruction.new(node.codeOrigin, - "andi", + "and" + tl, [node.operands[0], node.operands[1], tmp], node.annotation) list << Instruction.new(node.codeOrigin, @@ -503,6 +504,10 @@ def mipsLowerMisplacedAddresses(list) newList << Instruction.new(node.codeOrigin, node.opcode, riscAsRegisters(newList, [], node.operands, "b")) + when "andb" + newList << Instruction.new(node.codeOrigin, + "andi", + riscAsRegisters(newList, [], node.operands, "b")) when /^(bz|bnz|bs|bo)/ tl = $~.post_match == "" ? "i" : $~.post_match newList << Instruction.new(node.codeOrigin, |