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| author | Andreas Schwab <schwab@suse.de> | 2018-12-18 16:41:39 +0100 |
|---|---|---|
| committer | Allan Sandfeld Jensen <allan.jensen@qt.io> | 2019-04-29 13:49:26 +0000 |
| commit | 9a6a84731131b205f74b10f866ae212e0895bd4a (patch) | |
| tree | 7cfa41c8498fe3aa95d58981cfaa4f1dbe9c7ebf /src/corelib/global/qprocessordetection.h | |
| parent | 8059762565d1ed6b7aaee2729d3a637efcd671d5 (diff) | |
Add RISC-V detection
Change-Id: I0203c88e0944064841c9f6fe9f8a7888d6c421d1
Reviewed-by: Giuseppe D'Angelo <giuseppe.dangelo@kdab.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
Diffstat (limited to 'src/corelib/global/qprocessordetection.h')
| -rw-r--r-- | src/corelib/global/qprocessordetection.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/corelib/global/qprocessordetection.h b/src/corelib/global/qprocessordetection.h index 1f327c352e..8d65720850 100644 --- a/src/corelib/global/qprocessordetection.h +++ b/src/corelib/global/qprocessordetection.h @@ -282,6 +282,20 @@ // Q_BYTE_ORDER not defined, use endianness auto-detection /* + RISC-V family, known variants: 32- and 64-bit + + RISC-V is little-endian. +*/ +#elif defined(__riscv) +# define Q_PROCESSOR_RISCV +# if __riscv_xlen == 64 +# define Q_PROCESSOR_RISCV_64 +# else +# define Q_PROCESSOR_RISCV_32 +# endif +# define Q_BYTE_ORDER Q_LITTLE_ENDIAN + +/* S390 family, known variant: S390X (64-bit) S390 is big-endian. |