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authorAndreas Schwab <schwab@suse.de>2018-12-18 16:41:39 +0100
committerAllan Sandfeld Jensen <allan.jensen@qt.io>2019-04-29 13:49:26 +0000
commit9a6a84731131b205f74b10f866ae212e0895bd4a (patch)
tree7cfa41c8498fe3aa95d58981cfaa4f1dbe9c7ebf /src
parent8059762565d1ed6b7aaee2729d3a637efcd671d5 (diff)
Add RISC-V detection
Change-Id: I0203c88e0944064841c9f6fe9f8a7888d6c421d1 Reviewed-by: Giuseppe D'Angelo <giuseppe.dangelo@kdab.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/corelib/global/archdetect.cpp4
-rw-r--r--src/corelib/global/qglobal.cpp36
-rw-r--r--src/corelib/global/qprocessordetection.h14
3 files changed, 54 insertions, 0 deletions
diff --git a/src/corelib/global/archdetect.cpp b/src/corelib/global/archdetect.cpp
index 66a5e074f6..1d00b7f5a5 100644
--- a/src/corelib/global/archdetect.cpp
+++ b/src/corelib/global/archdetect.cpp
@@ -67,6 +67,10 @@
# define ARCH_PROCESSOR "power"
#elif defined(Q_PROCESSOR_POWER_64)
# define ARCH_PROCESSOR "power64"
+#elif defined(Q_PROCESSOR_RISCV_32)
+# define ARCH_PROCESSOR "riscv32"
+#elif defined(Q_PROCESSOR_RISCV_64)
+# define ARCH_PROCESSOR "riscv64"
#elif defined(Q_PROCESSOR_S390_X)
# define ARCH_PROCESSOR "s390x"
#elif defined(Q_PROCESSOR_S390)
diff --git a/src/corelib/global/qglobal.cpp b/src/corelib/global/qglobal.cpp
index d95064af27..16d8d8b8ac 100644
--- a/src/corelib/global/qglobal.cpp
+++ b/src/corelib/global/qglobal.cpp
@@ -1884,6 +1884,42 @@ bool qSharedBuild() noexcept
*/
/*!
+ \macro Q_PROCESSOR_RISCV
+ \relates <QtGlobal>
+ \since 5.13
+
+ Defined if the application is compiled for RISC-V processors. Qt currently
+ supports two RISC-V variants: \l Q_PROCESSOR_RISCV_32 and \l
+ Q_PROCESSOR_RISCV_64.
+
+ \sa QSysInfo::buildCpuArchitecture()
+*/
+
+/*!
+ \macro Q_PROCESSOR_RISCV_32
+ \relates <QtGlobal>
+ \since 5.13
+
+ Defined if the application is compiled for 32-bit RISC-V processors. The \l
+ Q_PROCESSOR_RISCV macro is also defined when Q_PROCESSOR_RISCV_32 is
+ defined.
+
+ \sa QSysInfo::buildCpuArchitecture()
+*/
+
+/*!
+ \macro Q_PROCESSOR_RISCV_64
+ \relates <QtGlobal>
+ \since 5.13
+
+ Defined if the application is compiled for 64-bit RISC-V processors. The \l
+ Q_PROCESSOR_RISCV macro is also defined when Q_PROCESSOR_RISCV_64 is
+ defined.
+
+ \sa QSysInfo::buildCpuArchitecture()
+*/
+
+/*!
\macro Q_PROCESSOR_S390
\relates <QtGlobal>
diff --git a/src/corelib/global/qprocessordetection.h b/src/corelib/global/qprocessordetection.h
index 1f327c352e..8d65720850 100644
--- a/src/corelib/global/qprocessordetection.h
+++ b/src/corelib/global/qprocessordetection.h
@@ -282,6 +282,20 @@
// Q_BYTE_ORDER not defined, use endianness auto-detection
/*
+ RISC-V family, known variants: 32- and 64-bit
+
+ RISC-V is little-endian.
+*/
+#elif defined(__riscv)
+# define Q_PROCESSOR_RISCV
+# if __riscv_xlen == 64
+# define Q_PROCESSOR_RISCV_64
+# else
+# define Q_PROCESSOR_RISCV_32
+# endif
+# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
+
+/*
S390 family, known variant: S390X (64-bit)
S390 is big-endian.