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authorThiago Macieira <thiago.macieira@intel.com>2021-12-15 19:44:58 -0300
committerThiago Macieira <thiago.macieira@intel.com>2022-01-20 20:48:23 -0300
commit970b249140da895abc23c3499ec11ccbf060fe00 (patch)
tree6dea3821060323a928e0e72e56d5bdc049069f66 /src
parentea10fe66e53188767c5090b3b25d5bb7732c73a8 (diff)
qsimd.h: move the rest of the __xxx__ definitions that MSVC lacks
The Intel compiler is now based on Clang, so it always defines the macros like Clang and GCC do, so we don't need to worry about it any more. We only need to define the macros that MSVC lacks. Change-Id: Ib42b3adc93bf4d43bd55fffd16c10f0f6fef43ef Reviewed-by: Lars Knoll <lars.knoll@qt.io> Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
Diffstat (limited to 'src')
-rw-r--r--src/corelib/global/qsimd.h18
-rw-r--r--src/corelib/global/qsimd_p.h29
2 files changed, 15 insertions, 32 deletions
diff --git a/src/corelib/global/qsimd.h b/src/corelib/global/qsimd.h
index 5fd34d0092..1f15c65594 100644
--- a/src/corelib/global/qsimd.h
+++ b/src/corelib/global/qsimd.h
@@ -1,7 +1,7 @@
/****************************************************************************
**
** Copyright (C) 2020 The Qt Company Ltd.
-** Copyright (C) 2018 Intel Corporation.
+** Copyright (C) 2022 Intel Corporation.
** Contact: https://www.qt.io/licensing/
**
** This file is part of the QtCore module of the Qt Toolkit.
@@ -89,20 +89,20 @@
# define QT_COMPILER_USES_mips_dspr2 -1
#endif
-#if defined(Q_PROCESSOR_X86)
-#if defined(Q_CC_MSVC)
+#if defined(Q_PROCESSOR_X86) && defined(Q_CC_MSVC)
// MSVC doesn't define __SSE2__, so do it ourselves
# if (defined(_M_X64) || _M_IX86_FP >= 2)
# define __SSE__ 1
# define __SSE2__ 1
# endif
-#if (defined(_M_AVX) || defined(__AVX__))
+# if (defined(_M_AVX) || defined(__AVX__))
// Visual Studio defines __AVX__ when /arch:AVX is passed, but not the earlier macros
// See: https://msdn.microsoft.com/en-us/library/b0084kay.aspx
# define __SSE3__ 1
# define __SSSE3__ 1
# define __SSE4_1__ 1
# define __SSE4_2__ 1
+# define __POPCNT__ 1
# ifndef __AVX__
# define __AVX__ 1
# endif
@@ -110,7 +110,15 @@
# ifdef __SSE2__
# define QT_VECTORCALL __vectorcall
# endif
-#endif
+# ifdef __AVX2__
+// MSVC defines __AVX2__ with /arch:AVX2
+# define __F16C__ 1
+# define __FMA__ 1
+# define __BMI__ 1
+# define __BMI2__ 1
+# define __LZCNT__ 1
+# endif
+// Starting with /arch:AVX512, MSVC defines all the macros
#endif
#if defined(Q_PROCESSOR_X86) && defined(__SSE2__)
diff --git a/src/corelib/global/qsimd_p.h b/src/corelib/global/qsimd_p.h
index 118a62e6ac..fdf5529135 100644
--- a/src/corelib/global/qsimd_p.h
+++ b/src/corelib/global/qsimd_p.h
@@ -198,33 +198,8 @@
# include <immintrin.h>
# endif
-# if defined(__SSE4_2__) && defined(QT_COMPILER_SUPPORTS_SIMD_ALWAYS) && (defined(Q_CC_INTEL) || defined(Q_CC_MSVC))
-// POPCNT instructions:
-// All processors that support SSE4.2 support POPCNT
-// (but neither MSVC nor the Intel compiler define this macro)
-# define __POPCNT__ 1
-# endif
-
-// AVX intrinsics
-# if defined(__AVX__) && defined(QT_COMPILER_SUPPORTS_SIMD_ALWAYS) && (defined(Q_CC_INTEL) || defined(Q_CC_MSVC))
-// PCLMULQDQ instructions:
-// All processors that support AVX support PCLMULQDQ
-// (but neither MSVC nor the Intel compiler define this macro)
-# define __PCLMUL__ 1
-# endif
-
-# if defined(__AVX2__) && defined(QT_COMPILER_SUPPORTS_SIMD_ALWAYS) && (defined(Q_CC_INTEL) || defined(Q_CC_MSVC))
-// F16C instructions:
-// All processors that support AVX2 support F16C:
-// (but neither MSVC nor the Intel compiler define this macro)
-# define __F16C__ 1
-# endif
-
-# if defined(__BMI__) && !defined(__BMI2__) && defined(Q_CC_INTEL)
-// BMI2 instructions:
-// All processors that support BMI support BMI2 (and AVX2)
-// (but neither MSVC nor the Intel compiler define this macro)
-# define __BMI2__ 1
+# if defined(Q_CC_GNU) && defined(__AVX2__) && (!defined(__BMI__) || !defined(__FMA__))
+# error "Please enable the BMI and FMA extensions; you probably want to use -march=haswell or -march=x86-64-v3 instead of -mavx2"
# endif
# include "qsimd_x86_p.h"