| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
| |
Change-Id: I1a6dba065c45bf732c0174ed0a6492cc80478985
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Futexes on Linux can be used across processes, for inter-process
synchronisation. The private flag tells the kernel that this futex is
not used with other processes, so it does not need to check for waiters
outside the current process.
This feature had been proposed in Merge Request 25, but was lost.
Change-Id: Ieafa8b8df0949bd9ae73709b3ec63f7709b0b2a6
Reviewed-by: João Abecasis <joao.abecasis@nokia.com>
|
|
|
|
|
| |
Change-Id: I7659ce312f3777ae68190979681656d12306d33c
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
|
|
|
|
|
|
|
|
|
|
|
| |
The qt_global_mutexpool was private API deprecated long time ago.
And there is no reason to call qt_create_tls because it is called in
QThreadData::current that is called from the QObject constructor, even
before QCoreApplication::init can be called.
Change-Id: Idf3576d8591377811b727b12edc43dc898570ba4
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
|
|
|
|
|
| |
Change-Id: Ie079aea3412a53cf9dccaa770fa64ff5b6b7b3b1
Reviewed-by: Stephen Kelly <stephen.kelly@kdab.com>
|
|
|
|
|
|
|
|
|
|
|
| |
Naming threads is very useful for release builds.
Enabling only on Linux/Mac for now.
The Windows port is using debugger specific API for setting thread
names, so it has to remain debug mode only.
Change-Id: I179521f65f215ff038e8230f958f6aa728ea4cbe
Reviewed-by: Lars Knoll <lars.knoll@nokia.com>
Reviewed-by: João Abecasis <joao.abecasis@nokia.com>
|
|\
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Conflicts:
dist/changes-5.0.0
mkspecs/features/qt_module_config.prf
qmake/project.cpp
qmake/property.cpp
Change-Id: I6e4af40743a9aeff8ed18533a48036e332acc296
|
| |
| |
| |
| |
| | |
Change-Id: Iad2d60d1abe363a3b85eaf152861d0979a997d81
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|/
|
|
|
|
|
|
|
|
|
| |
QDoc now has support for Doxygen style commands for italics, bold
and list items. This change applies that change in QDoc to the
actual documentation.
Task-number: QTBUG-24578
Change-Id: I519bf9c29b14092e3ab6067612f42bf749eeedf5
Reviewed-by: Shane Kearns <shane.kearns@accenture.com>
Reviewed-by: Lars Knoll <lars.knoll@nokia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Don't register the thread handle and QThread object pointer to watch list
for adopted thread watcher thread in Windows. Otherwise the watcher thread
will never exit and can't clean up its own QThreadData and QAdoptedThread
object.
Task-number: QTBUG-23961
Change-Id: Ia84326cf3cfd978d2b003ccc1bb6861db950e899
Reviewed-by: Friedemann Kleint <Friedemann.Kleint@nokia.com>
Reviewed-by: Joerg Bornemann <joerg.bornemann@nokia.com>
|
|
|
|
|
|
| |
Change-Id: Ib44ee9739499ba4c5f0fecbef3976251ea22836d
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Fix potential race condition in data structure of adopted thread watcher
in Windows. Since QVector is not thread safe, it is not safe to read and
append data to qt_adopted_thread_handles or qt_adopted_qthread
simultaneously in qthread_win.cpp. This patch fix this race condition.
Change-Id: I2d0c7a4cdde5390d38d15c98343f0fc6ddd24aba
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
Reviewed-by: Friedemann Kleint <Friedemann.Kleint@nokia.com>
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
|
|
|
|
|
|
|
| |
As requested by Thiago
Change-Id: Ie5b00cf4e530e19d360d0bc588f0f051e04b338f
Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
|
|
|
|
|
|
|
|
| |
LSB doesn't allow syscalls, so fall back to the normal _unix
implementation
Change-Id: I8aba6147da8b46e3f85b0454cf9aca219811c9fe
Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
|
|
|
|
|
|
|
|
|
| |
IBM's POWER and the PowerPC architecture have been merged into a single
ISA, the Power ISA (see http://www.power.org). Use this unified name in
Qt.
Change-Id: Ia41492b0031d890843e43c5f7ecd1e60c65bb75b
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
This provides a fallback implementation on UNIX when the Q_PROCESSOR_*
and Q_CC_*/Q_COMPILER_* checks fail to find an implementation.
Note that we always compile qatomic_unix.cpp, but code is only included
when QATOMIC_UNIX_H is defined (meaning the checks above did not find an
implementation).
Change-Id: I8ce047847206003b4fa96eb3fb76b1c2ffbc2dfc
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Make qbasicatomic.h include the OS/compiler/processor dependent
implementation.
For implementations that have not yet been ported to declare a
QAtomicOps, they need to #include <QtCore/qoldbasicatomic.h>, and the
new QBasicAtomicInteger and QBasicAtomicPointer should not be declared.
Change-Id: Ia951834484c9f8dfa75131592e5e716b68ff989b
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
| |
This header is not used on Windows anymore, so remove the dead #ifdefs.
Change-Id: I76cfbd13c9fff0eab87cc69e8ca1e0d5ccab9e3a
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
|
|
|
|
| |
This architecture is obsolete and discontinued.
Support for PA-RISC can be re-added if needed, but it would be preferred
to use the GCC intrinsic support from qatomic_gcc.h (on Linux/HPPA, for
example).
Change-Id: I952e521a2c8c68840df0d44843b5487d5c20b135
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
|
| |
Thanks to João's help.
Change-Id: I9ad3035f016945bed9fdf425fc7b7edd5d20822d
Reviewed-by: João Abecasis <joao.abecasis@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
|
|
|
| |
Use the new Q_PROCESSOR_* macros to decide which headers to include in
the atomic implementation. This also removes qatomic_arm.h, which isn't
needed anymore, just select the correct qatomic_armv*.h from
qbasicatomic.h
Change-Id: I954848feafb8c420949d066ffcee1dd2b271e13b
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
|
|
|
| |
Most of these headers are either forwarding headers, or we explicitly
stop syncqt so that it doesn't generate class includes for the atomic
implementation. Either way, syncqt doesn't see the QT_END_* (and
sometimes not QT_BEGIN_*), which this commit fixes.
Change-Id: Icc8da6f384f38b1ff4eb265c731ce2f2ed92a1a3
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
| |
Task-number: QTBUG-20892
Change-Id: I614500aafb6428915509983608bbb0ade4e4f016
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
| |
qatomic_cxx0x.h doesn't exist.
Change-Id: Iac654ecf09a1b890d25fa23625c8c43f2f7f1ecf
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
|
|
|
| |
The QT_ARCH_WINDOWS(CE) define(s) aren't used to control which
header to include anymore, so just remove it. We also do not need
the empty src/corelib/arch/windows/arch.pri.
Change-Id: I5400fc852af31907e533d0278540b8cd3da391cb
Reviewed-by: Friedemann Kleint <Friedemann.Kleint@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
First, we do not need to have the QT_INTERLOCKED_REMOVE_VOLATILE(a)
macro anymore either, since the value stored in QBasicAtomicInteger is
not volatile.
Windows provides Interlocked*Pointer() functions in some configurations,
so we provide a partial specialization of QAtomicOps for pointer types.
For integer types, QAtomicOps selects an implementation based on the
size of the type. At the moment, we only support 32-bit types, but it
will be possible to add 64-bit later.
Note that the 32-bit specialization of QAtomicOpsBySize declares the
Type typedef as long, not int, since the Windows Interlocked*() API
takes parameters as longs and long pointers. Since this typedef differs
from the type given to QBasicAtomicInteger<T> by the QBasicAtomicInt
typedef, we need to templatise the _q_value parameter separately from
the other arguments in QGenericAtomicOps.
This templatisation would be necessary to port other architectures, such
as PA_RISC, where we need to have an int[4] array in the atomic type
while the arguments do not need this array.
Change-Id: Id71fa1ae334da2023553cb402b45e6c285f1d344
Reviewed-by: Friedemann Kleint <Friedemann.Kleint@nokia.com>
Reviewed-by: João Abecasis <joao.abecasis@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
QBasicMutex is a POD and can be used as a static global object.
in qpicture.cpp factoryLoader is used only once, and under the mutex, so
there is no need for Q_GLOBAL_STATIC for it, it can be a function static
in qhostinfo_unix.cpp the code seemed wrong while compiled with
namespace and QT_NO_GETADDRINFO. I also could get rid of one include
because it was included earlier.
Change-Id: I3c700203c3e067266c20733f4bda8031446dbb86
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
- Always use <qt_windows.h> as the last file to be included.
- Remove it from some headers, use Qt::HANDLE instead of HANDLE.
- Clean up #ifdef, use Q_OS_WIN for Windows/Windows CE.
- Add NOMINMAX to qt_windows.h to avoid problems with the
min/max macros.
- Remove <windows.h> from qplatformdefs.h (VS2005)
Change-Id: Ic44e2cb3eafce38e1ad645c3bf85745439398e50
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
Reviewed-by: Joerg Bornemann <joerg.bornemann@nokia.com>
|
|
|
|
|
|
|
|
|
|
| |
As in the past, to avoid rewriting various autotests that contain
line-number information, an extra blank line has been inserted at the
end of the license text to ensure that this commit does not change the
total number of lines in the license header.
Change-Id: I311e001373776812699d6efc045b5f742890c689
Reviewed-by: Rohan McGovern <rohan.mcgovern@nokia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The C++11 std::atomic type is very close to our API, to the point one
has to wonder if the committe was inspired by it. It provides all of
the memory semantics that Qt requires and more, plus some
compare-and-swap operations that we don't use.
The idea of returning the actual value in the event of a failed
compare-and-swap is actually quite good, as often we'll retry with
it. We just couldn't come up with a good name (fetchAndTestAndSet?).
The C++11 atomics require that the compiler support constexpr as well,
since std::atomic itself isn't required by the standard to be
trivially-constructible (in fact, it has a constexpr constructor in
the standard). For that reason, we need constexpr so we can add a
constructor to QBasicAtomic too.
Change-Id: I12c51455ba73350a6f7501aacc2ca7681c4369dd
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
With this implementation, we can have Qt run on any architecture that
GCC supports without having to write specialised code. However, on
some architectures, the code that GCC generates is not optimal: it
uses locking on ARMv5 and it's always fully-ordered. For that reason,
it appears after the Qt native assembly implementations (it's a
fallback, not an override).
Since they all have fully-ordered memory semantics, we define only the
xxxRelaxed functions. The exception is __sync_lock_and_test, which has
acquire semantics, so we need to define the Release and Ordered
versions too.
On some architectures, GCC can support atomics on types different than
32-bit and pointer-sized (like x86, x86-64, ARM and even
MIPS). However, there's no standardised way of telling: GCC seems to
define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2,4,8} if those operations
are present, but I couldn't find it on the ARM compiler (it was there
for i386, x86-64, IA-64 and MIPS).
Change-Id: I55ff7a7c0cfc6388b7ad8e2c0dedecffdf2a3e01
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
|
|
|
|
|
| |
Change-Id: I360c94d41691a618f1bec97da8317c9dcee658c0
Reviewed-by: Lars Knoll <lars.knoll@nokia.com>
|
|
|
|
|
|
|
|
|
|
| |
These defines were there to aid in the commercial
licensing scheme we used long ago, and are no longer needed.
Keep a QT_MODULE(x) define so other modules continue compiling.
Change-Id: I8fd76cd5270df8f14aee746b6cf32ebf7c23fec7
Reviewed-by: Lars Knoll <lars.knoll@nokia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The IA-64 architecture supports the actual memory ordering semantics
in many instructions, but not all. We actually implement the functions
for all operations, so we get the best possible output.
It does support proper load-acquire and store-release semantics, but
we don't need instructions for it: the ABI requires that a volatile
load be acquire and a volatile store be release.
The Intel and HP compiler codepaths are rewritten, but untested.
Change-Id: I7aa62a4ec65f63a97d1bbd8418bb2492c2be465f
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The LL/SC instructions are only present on MIPS II and up, so don't
pretend to support MIPS I. The previous implementation emitted the
instructions by telling the assembler to change instruction sets. Now,
the user must pass an -march= option to GCC telling it which
architecture or processor is being targetted.
On MIPS64, the 64-bit implementation allows supporting for long long
too.
Change-Id: I6dae6f8f61e563aba6a663227d91c5ddf554aa6a
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The implementation is divided in two files, as it used to be in the
previous implementation: one for ARMv5, one for ARMv6 and up.
For the ARMv5 implementation:
Drop the non-Linux EABI version of the atomics, as it's not
ABI-compatible with the ARMv6 and ARMv7 implementations. This
means this ARMv5 implementation only works on Linux. If other
systems implement kernel helpers like Linux, they can be added
too.
We use the __kernel_cmpxchg located at 0xffff0fc0 to implement the
operations, except for fetchAndStore, for which we use the SWP
instruction.
Also introduce the use of __kernel_dmb (at 0xffff0fa0) for the
memory barrier. Now this code is SMP-safe even when built with
ARMv5.
The kernel cmpxchg helper was introduced in Linux 2.6.12, whereas
the dmb helper was introduced in 2.6.15. That means 2.6.15 is the
minimum version now.
For ARMv6 and up:
Introduce byte, half-word and doubleword atomics that work on
ARMv6K and up.
For ARMv6 specifically, the memory barrier instruction (DMB) isn't
present, so we need to accomplish the same with the MCR
coprocessor instruction.
Change-Id: Ife7f9b920bcc7d1eef7611761f6c59ea940ec7df
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Both implementations now are very similar to one another, to the point
we could share the code if we wanted to. They are based on assembly
code for the Relaxed functions only, as the i386 and x86-64
architectures only allow for full memory ordering or something that
closely resembles it (see 8.2 "Memory ordering" in the Intel 64 and
IA-32 Architectures Software Developer's Manual Volume 3A). We could
add "lfence/mfence/sfence" in future versions if we wanted to (SSE2+).
Change-Id: I76966d9f8694edfece2c5ebd3387348fac721447
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The code is now much simpler and much more complete. Now the bootstrap
atomics (which aren't atomic at all) contain the full set of
operations.
The only integer supported is int, but all others would work too.
Change-Id: Id99f07818f9da059c4ff02520f9cbf2d1a71a514
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
| |
Replace Nokia contact email address with Qt Project website.
Change-Id: I431bbbf76d7c27d8b502f87947675c116994c415
Reviewed-by: Rohan McGovern <rohan.mcgovern@nokia.com>
|
|
|
|
|
|
|
|
| |
Contact point is the Qt Project, and needs to be included for
all new files added to the repository.
Change-Id: Id0e7219e1d11a169f1a91439728cbda55ab29eeb
Reviewed-by: Lars Knoll <lars.knoll@nokia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
QBasicAtomicPointer is forward declared as a class, keep the actual
declaration of QBasicAtomicInteger and QBasicAtomicPointer as class with
all public members (qoldbasicatomic.h does the same).
src/corelib/thread/qbasicatomic.h:158:1: warning:
'QBasicAtomicPointer' defined as a struct template here but
previously declared as a class template [-Wmismatched-tags]
struct QBasicAtomicPointer
^
src/corelib/global/qglobal.h:1861:23: note: did you mean struct here?
template <typename T> class QBasicAtomicPointer;
^~~~~
struct
Change-Id: I38c59c29d7f796dde772e7f403bbf98b04571a08
Reviewed-by: Lars Knoll <lars.knoll@nokia.com>
|
|
|
|
|
|
|
|
|
|
| |
Public headers should compile with QT_NO_KEYWORDS defined.
Change-Id: I5620b4b2600f5e39bb402b97d14fdb257dfe9942
Reviewed-by: Robin Burchell <robin+qt@viroteck.net>
Reviewed-by: Jonas Gastal <jgastal@profusion.mobi>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
Reviewed-by: Lars Knoll <lars.knoll@nokia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The new implementation is API- and ABI-compatible with the old
implementation, provided that QBasicAtomicInt isn't used as an
argument in a function call or the return value: now, QBasicAtomicInt
is a typedef to QBasicAtomicInteger<int>.
The new design is based on CRTP: the QGenericAtomicOps template class
takes as a template parameter the derived class itself. This way, we
implement a "poor man's virtual" without a virtual table and
everything is inline.
QGenericAtomicOps implements most of the atomics code that is repeated
in many classes all over:
* Acquire semantics are obtained by placing an acquire barrier after
the Relaxed operation
* Release semantics are obtained by placing a release barrier before
the Relaxed operation
* Ordered semantics are obtained by placing an ordered barrier before
the Relaxed operation (either way would be fine)
* fetchAndStoreRelaxed and fetchAndAddRelaxed are implemented on top
of testAndSetRelaxed
* ref and deref are implemented on top of fetchAndAddRelaxed
It also adds load, loadAcquire, store and storeRelease: the default
implementations of loadAcquire and storeRelease operate on a volatile
variable and add barriers. There are no direct operators for accessing
the value.
Each architecture-specific implementation can override any of the
functions or the memory barrier functions. It must implement at least
the testAndSetRelaxed function.
In addition, by specialising one template class, the implementations
can allow QBasicAtomicInteger for additional types (of different
sizes). At the very least, int, unsigned and pointers must be supported.
Change-Id: I6da647e225bb330d3cfc16f84d0e7849dff85ec7
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
|
|
|
|
|
|
| |
Change-Id: I15df58f9dc29189419f8cbc0ce47bf11e9f17cf4
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
| |
Change-Id: I02f2c620296fcd91d4967d58767ea33fc4e1e7dc
Reviewed-by: Rohan McGovern <rohan.mcgovern@nokia.com>
|
|
|
|
|
| |
Change-Id: Iabc7c6a9f5554450e766dc63f518595871a3abb7
Reviewed-by: Richard J. Moore <rich@kde.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This provides a ~10% improvement to the newly introduced QCoreApplication
event_posting_benchmark (a simple synthetic benchmark of creating a bunch of
events, posting them, and sending the queue).
before:
********* Start testing of QCoreApplicationBenchmark *********
Config: Using QTest library 5.0.0, Qt 5.0.0
PASS : QCoreApplicationBenchmark::initTestCase()
RESULT : QCoreApplicationBenchmark::signal_slot_benchmark():"1000":
0.82 msecs per iteration (total: 53, iterations: 64)
RESULT : QCoreApplicationBenchmark::signal_slot_benchmark():"10000":
8.6 msecs per iteration (total: 69, iterations: 8)
RESULT : QCoreApplicationBenchmark::signal_slot_benchmark():"100000":
84 msecs per iteration (total: 84, iterations: 1)
RESULT : QCoreApplicationBenchmark::signal_slot_benchmark():"1000000":
874 msecs per iteration (total: 874, iterations: 1)
PASS : QCoreApplicationBenchmark::signal_slot_benchmark()
PASS : QCoreApplicationBenchmark::cleanupTestCase()
Totals: 3 passed, 0 failed, 0 skipped
********* Finished testing of QCoreApplicationBenchmark *********
after:
********* Start testing of QCoreApplicationBenchmark *********
Config: Using QTest library 5.0.0, Qt 5.0.0
PASS : QCoreApplicationBenchmark::initTestCase()
RESULT : QCoreApplicationBenchmark::event_posting_benchmark():"1000 events":
0.781 msecs per iteration (total: 100, iterations: 128)
RESULT : QCoreApplicationBenchmark::event_posting_benchmark():"10000 events":
7.8 msecs per iteration (total: 63, iterations: 8)
RESULT : QCoreApplicationBenchmark::event_posting_benchmark():"100000 events":
75 msecs per iteration (total: 75, iterations: 1)
RESULT : QCoreApplicationBenchmark::event_posting_benchmark():"1000000 events":
774 msecs per iteration (total: 774, iterations: 1)
PASS : QCoreApplicationBenchmark::event_posting_benchmark()
PASS : QCoreApplicationBenchmark::cleanupTestCase()
Totals: 3 passed, 0 failed, 0 skipped
********* Finished testing of QCoreApplicationBenchmark *********
Change-Id: Ibf56d9526b0a8cbaf171008da4104bb457628172
Reviewed-by: Sergio Ahumada <sergio.ahumada@nokia.com>
|
|
|
|
|
| |
Change-Id: I3b569b1240a0bc5b2589de353dbf62c175472448
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
After commit 79f675a1e0f628bbc25345ebc1eb1f5809166c6b, the connect and
disconnect callback API effectively becomes useless. Now that these
callbacks cannot/do not, it makes little sense to keep the backdoors
added for Qt Jambi support.
Remove them for now. Should the Qt Jambi team want/need to port to Qt 5,
we can re-add them, possibly designing a better API for doing so as
well.
Change-Id: I6209a1d647d683c979d5294b632b8c12c0f9f91c
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
Reviewed-by: Lars Knoll <lars.knoll@nokia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This is a source incompatible change. There is concern that the
convenience of the implicit cast and assignment operators can lead to
misuse. Several commits have already been done that remove excess use
of the implicit cast, which is a *volatile* read every time it's used.
Users of the QAtomic* API should have to think about when they are
loading the value, and if they do or don't need the acquire memory
barrier on load. The code that people would write using this API is
meant to be multi-threaded, concurrent, and correct. The API should not
allow them to inadvertently, possibly unknowingly, shoot themselves
in the foot.
SC-break-rubber-stamped-by: Lars Knoll
Change-Id: I88fbc26d9db7b5ec80a58ad6271ffa13bbfd191f
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
|